Magdy A. El-Moursy

Orcid: 0000-0002-9890-4651

According to our database1, Magdy A. El-Moursy authored at least 58 papers between 2003 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2022
Energy-Efficient Precision-Scaled CNN Implementation With Dynamic Partial Reconfiguration.
IEEE Access, 2022

2020
PMSMC: Priority-based Multi-requestor Scheduler for Embedded System Memory Controller.
J. Parallel Distributed Comput., 2020

Traffic Signs Detection and Recognition System using Deep Learning.
CoRR, 2020

Energy Adaptive Convolution Neural Network Using Dynamic Partial Reconfiguration.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019
Dual-Channel Multiplier for Piecewise-Polynomial Function Evaluation for Low-Power 3-D Graphics.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A robust, real-time and calibration-free lane departure warning system.
Microprocess. Microsystems, 2019

CFPA: Congestion aware, fault tolerant and process variation aware adaptive routing algorithm for asynchronous Networks-on-Chip.
J. Parallel Distributed Comput., 2019

Fast Transaction-Level Model for Direct Memory Access Controller.
J. Circuits Syst. Comput., 2019

Virtual Verification and Validation of Automotive System.
J. Circuits Syst. Comput., 2019

Brain-in-Car: A Brain Activity-based Emotion Recognition Embedded System for Automotive.
Proceedings of the IEEE International Conference of Vehicular Electronics and Safety, 2019

2018
Dynamic power estimation using Transaction Level Modeling.
Microelectron. J., 2018

Virtual Electronic Control Unit as a Functional Mockup Unit for Heterogeneous Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Double Logarithmic Arithmetic Technique for Low-Power 3-D Graphics Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Architecture level analysis for process variation in synchronous and asynchronous Networks-on-Chip.
J. Parallel Distributed Comput., 2017

System-level simulator for process variation influenced synchronous and asynchronous NoCs.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

TLM Virtual Platform for Fast and Accurate Power Estimation.
Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017

Accurate piecewise uniform approximation logarithmic/antilogarithmic converters for GPU applications.
Proceedings of the 29th International Conference on Microelectronics, 2017

2016
Process Variation Delay and Congestion Aware Routing Algorithm for Asynchronous NoC Design.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Direct computation for high performance interpolation filter.
Microelectron. J., 2016

Corrigendum to "High throughput asynchronous NoC design under high process variation" [Integr. VLSI J. (2015) 1-13].
Integr., 2016

Lane departure warning tracking system based on score mechanism.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Transaction Level Power Modeling (TLPM) Methodology.
Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016

High performance interpolation filter using direct computation.
Proceedings of the 11th International Design & Test Symposium, 2016

2015
Traffic-Based Virtual Channel Activation for Low-Power NoC.
IEEE Trans. Very Large Scale Integr. Syst., 2015

High Throughput Asynchronous NoC Design under High Process Variation.
Integr., 2015

Analysis and design of Network on Chip under high process variation.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Optimization for traffic-based virtual channel activation low-power NoC.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015

Novel Routing Algorithm for Minimum on Delay with Process Variation and Congestion in Asynchronous NoC.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Low-Power NoC Using Optimum Adaptation.
Proceedings of the Computational Intelligence in Digital and Network Designs and Applications, 2015

2014
High speed special function unit for graphics processing unit.
Proceedings of the 9th International Design and Test Symposium, 2014

Efficient embedded SoC hardware/software codesign using virtual platform.
Proceedings of the 9th International Design and Test Symposium, 2014

2013
Interconnect Modeling with the existence of Line inductance.
J. Circuits Syst. Comput., 2013

Ultra-Fast DMAC TLM Model for High Speed Virtual Platform Simulation.
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013

Traffic-based virtual channel activation for low-power NoC.
Proceedings of the 8th International Design and Test Symposium, 2013

High throughput asynchronous NoC switch for high process variation.
Proceedings of the 8th International Design and Test Symposium, 2013

Asynchronous high throughput NoC under high process variation.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
Low leakage power NoC switch using AVC.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A low power programmable FIR filter using sharing multiplication technique.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011
Asynchronous switching for low-power networks-on-chip.
Microelectron. J., 2011

TLM Based Approach for Architecture Exploration of Multicore Systems-on-Chip.
Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011

Novel Adaptive Virtual Channels technique for NoC switch.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

2010
Modeling of RLC interconnect lines.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Power characteristics of Networks on Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Asynchronous BFT for low power networks on chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

High speed low power composite field SBOX.
Proceedings of the 5th International Design and Test Workshop, 2010

2009
High throughput architecture for CLICHÉ Network on Chip.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

High Throughput Architecture for High Performance NoC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Power efficient Networks on Chip.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

High Throughput architecture for OCTAGON Network on Chip.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2007
Wire shaping of RLC interconnects.
Integr., 2007

2006
Optimum wire tapering for minimum power dissipation in RLC interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Exponentially tapered H-tree clock distribution networks.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Shielding effect of on-chip interconnect inductance.
IEEE Trans. Very Large Scale Integr. Syst., 2005

2004
Power characteristics of inductive interconnect.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Optimum wire sizing of <i>RLC</i> interconnect with repeaters .
Integr., 2004

2003
1-V ADPCM Processor for Low-Power Wireless Applications.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Inductive interconnect width optimization for low power.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Optimum wire sizing of RLC interconnect with repeaters.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003


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