Dominic DiTomaso

According to our database1, Dominic DiTomaso authored at least 22 papers between 2011 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Sustainability in Network-on-Chips by Exploring Heterogeneity in Emerging Technologies.
IEEE Trans. Sustain. Comput., 2019

Machine learning enabled power-aware Network-on-Chip design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Dynamic error mitigation in NoCs using intelligent prediction techniques.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Exploring Wireless Technology for Off-Chip Memory Access.
Proceedings of the 24th IEEE Annual Symposium on High-Performance Interconnects, 2016

Secure Model Checkers for Network-on-Chip (NoC) Architectures.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

A-WiNoC: Adaptive Wireless Network-on-Chip Architecture for Chip Multiprocessors.
IEEE Trans. Parallel Distributed Syst., 2015

A New Frontier in Ultralow Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures.
IEEE Trans. Computers, 2015

Kilo-core Wireless Network-on-Chips (NoCs) Architectures.
Proceedings of the Second Annual International Conference on Nanoscale Computing and Communication, 2015

QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Energy-efficient adaptive wireless NoCs architecture.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

On ultra-short wireless interconnects for NoCs and SoCs: Bridging the 'THz Gap'.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Design of a Concentrated Torus Topology with Channel Buffers and Efficient Crossbars in NoCs.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Wireless networks-on-chips: architecture, wireless channel, and devices.
IEEE Wirel. Commun., 2012

Energy efficient modulation for a wireless network-on-chip architecture.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Evaluation and performance analysis of energy efficient wireless NoC architecture.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Evaluation of fault tolerant channel buffers for improving reliability in NoCs.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Energy-Efficient and Fault-Tolerant Unified Buffer and Bufferless Crossbar Architecture for NoCs.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Power efficient photonic networks for many-core architectures.
Proceedings of the 2012 International Green Computing Conference, 2012

Co-design of channel buffers and crossbar organizations in NoCs architectures.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture.
Proceedings of the IEEE 19th Annual Symposium on High Performance Interconnects, 2011