Travis Boraten

Orcid: 0000-0002-1627-7069

According to our database1, Travis Boraten authored at least 10 papers between 2012 and 2023.

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Bibliography

2023

2018
Runtime Techniques to Mitigate Soft Errors in Network-on-Chip (NoC) Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Mitigation of Hardware Trojan based Denial-of-Service attack for secure NoCs.
J. Parallel Distributed Comput., 2018

Securing NoCs Against Timing Attacks with Non-Interference Based Adaptive Routing.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

2016
Dynamic error mitigation in NoCs using intelligent prediction techniques.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Mitigation of Denial of Service Attack with Hardware Trojans in NoC Architectures.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

Secure Model Checkers for Network-on-Chip (NoC) Architectures.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Packet security with path sensitization for NoCs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2013
Energy-efficient Runtime Adaptive Scrubbing in fault-tolerant Network-on-Chips (NoCs) architectures.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012
Evaluation of fault tolerant channel buffers for improving reliability in NoCs.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012


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