Donald L. Dietmeyer

According to our database1, Donald L. Dietmeyer authored at least 25 papers between 1963 and 1998.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Bibliography

1998
Exploiting near symmetry in multilevel logic synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1993
Generating minimal covers of symmetric functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992
Multilevel logic synthesis with extended arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Three Decades of HDLs: Part I, CDL Through TI-HDL.
IEEE Des. Test Comput., 1992

1991
Multilevel logic synthesis of symmetric switching functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

1987
Local Transformations via Cube Operations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

1983
CONLAN Report
Lecture Notes in Computer Science 151, Springer, ISBN: 3-540-12275-3, 1983

1980
An Overview of CONLAN: A Formal Construction Method for Hardware Description Language.
Proceedings of the Information Processing, Proceedings of the 8th IFIP Congress 1980, Tokyo, Japan - October 6-9, 1980 and Melbourne, Australia, 1980

CONLAN: a formal construction method for hardware description languages: language application.
Proceedings of the American Federation of Information Processing Societies: 1980 National Computer Conference, 1980

CONLAN: a formal construction method for hardware description languages: language derivation.
Proceedings of the American Federation of Information Processing Societies: 1980 National Computer Conference, 1980

CONLAN: a formal construction method for hardware description languages: basic principles.
Proceedings of the American Federation of Information Processing Societies: 1980 National Computer Conference, 1980

1974
Introducing DDL.
Computer, 1974

1973
Fast State Minimization of Incompletely Specified Sequential Machines.
IEEE Trans. Computers, 1973

1971
The Avoidance and Elimination of Function Hazards in Asynchronous Sequential Circuits.
IEEE Trans. Computers, 1971

1969
Computer Reduction of Two-Level, Multiple-Output Switching Circuits.
IEEE Trans. Computers, 1969

Translation of a DDL Digital System Specification to Boolean Equations.
IEEE Trans. Computers, 1969

Logic Design Automation of Fan-In Limited NAND Networks.
IEEE Trans. Computers, 1969

1968
An Algorithm for Synthesis of Multiple-Output Combinational Logic.
IEEE Trans. Computers, 1968

A Digital System Design Language (DDL).
IEEE Trans. Computers, 1968

Bounds on the Period of Oscillatory Activity in Randomly Interconnected Networks of Neuron-Like Elements.
IEEE Trans. Computers, 1968

Generating prime implicants via ternary encoding and decimal arithmetic.
Commun. ACM, 1968

1967
Identification of Symmetry, Redundancy and Equivalence of Boolean Functions.
IEEE Trans. Electron. Comput., 1967

1965
A Computer-Oriented Factoring Algorithm for NOR Logic Design.
IEEE Trans. Electron. Comput., 1965

1963
Conversion from Positive to Negative and Imaginary Radix.
IEEE Trans. Electron. Comput., 1963

A Magnetic Ternary Device.
IEEE Trans. Electron. Comput., 1963


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