Dominique Borrione

According to our database, Dominique Borrione authored at least 72 papers between 1976 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Mining Missing Assumptions from Counter-Examples.

Guillaume Plassan, Katell Morin-Allory, Dominique Borrione

ACM Trans. Embed. Comput. Syst., 2019

2017

Synthesis of Regular Expressions Revisited: From PSL SEREs to Hardware.

Fatemeh Negin Javaheri, Katell Morin-Allory, Dominique Borrione

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Extraction of missing formal assumptions in under-constrained designs.

Guillaume Plassan, Katell Morin-Allory, Dominique Borrione

Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2017

2016

Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings.

Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Shaker Sarwary, Dominique Borrione

Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Conclusively verifying clock-domain crossings in very large hardware designs.

Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Fahim Rahim, Shaker Sarwary, Dominique Borrione

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

2015

Efficient and Correct by Construction Assertion-Based Synthesis.

Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione

IEEE Trans. Very Large Scale Integr. Syst., 2015

Enabler-based synchronizer model for clock domain crossing static verification.

Mejid Kebaili, Katell Morin-Allory, Jean-Christophe Brignone, Dominique Borrione

Proceedings of the 2015 Forum on Specification and Design Languages, 2015

2014

A tool for the automatic TLM-to-RTL conversion of embedded systems requirements for a seamless verification flow.

Zeineb Bel Hadj Amor, Laurence Pierre, Dominique Borrione

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

2013

SyntHorus-2: Automatic prototyping from PSL.

Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Fast prototyping from assertions: A pragmatic approach.

Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione

Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

Application of formal methods for design space exploration and refinement.

Dominique Borrione, Ashraf M. Salem

Proceedings of the 2013 Forum on specification and Design Languages, 2013

2010

Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers.

Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009

A Formal Approach to the Verification of Networks on Chip.

Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz

EURASIP J. Embed. Syst., 2009

From Assertion-Based Verification to Assertion-Based Synthesis.

Yann Oddos, Katell Morin-Allory, Dominique Borrione

Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009

MYGEN: automata-based on-line test generator for assertion-based verification.

Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

High-level symbolic simulation for automatic model extraction.

Florent Ouchet, Dominique Borrione, Katell Morin-Allory, Laurence Pierre

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008

A functional formalization of on chip communications.

Julien Schmaltz, Dominique Borrione

Formal Aspects Comput., 2008

Executable formal specification and validation of NoC communication infrastructures.

Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Assertion-Based Design with Horus.

Yann Oddos, Katell Morin-Allory, Dominique Borrione

Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

Proving and disproving assertion rewrite rules with automated theorem provers.

Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

2007

Synthesis of Property Monitors for Online Fault Detection.

Katell Morin-Allory, Eric Gascard, Dominique Borrione

J. Circuits Syst. Comput., 2007

A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study.

Dominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz

Proceedings of the First International Symposium on Networks-on-Chips, 2007

Asynchronous online-monitoring of logical and temporal assertions.

Katell Morin-Allory, Laurent Fesquet, Benjamin Roustan, Dominique Borrione

Proceedings of the Forum on specification and Design Languages, 2007

Prototyping Generators for On-line Test Vector Generation Based on PSL Properties.

Yann Oddos, Katell Morin-Allory, Dominique Borrione

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

On-Line Test Vector Generation from Temporal Constraints Written in PSL.

Yann Oddos, Katell Morin-Allory, Dominique Borrione

Proceedings of the IFIP VLSI-SoC 2006, 2006

Asynchronous Assertion Monitors for multi-Clock Domain System Verification.

Katell Morin-Allory, Laurent Fesquet, Dominique Borrione

Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

On-line Monitoring of Properties Built on Regular Expressions.

Katell Morin-Allory, Dominique Borrione

Proceedings of the Forum on specification and Design Languages, 2006

Proven correct monitors from PSL specifications.

Katell Morin-Allory, Dominique Borrione

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Formalizing On Chip Communications in a Functional Style.

Julien Schmaltz, Dominique Borrione

Proceedings of the Workshop "Trustworthy Software" 2006, 2006

Towards a formal theory of on chip communications in the ACL2 logic.

Julien Schmaltz, Dominique Borrione

Proceedings of the Sixth International Workshop on the ACL2 Theorem Prover and its Applications, 2006

2005

Formal Verification of a SHA-1 Circuit Core Using ACL2.

Diana Toma, Dominique Borrione

Proceedings of the Theorem Proving in Higher Order Logics, 18th International Conference, 2005

A Generic Network on Chip Model.

Julien Schmaltz, Dominique Borrione

Proceedings of the Theorem Proving in Higher Order Logics, 18th International Conference, 2005

A proof of correctness for the construction of property monitors.

Katell Morin-Allory, Dominique Borrione

Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning.

Ghiath Al Sammane, Dominique Borrione, Remy Chevallier

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004

TheoSim: combining symbolic simulation and theorem proving for hardware verification.

Ghiath Al Sammane, Julien Schmaltz, Diana Toma, Pierre Ostier, Dominique Borrione

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

A Functional Approach to the Formal Specification of Networks on Chip.

Julien Schmaltz, Dominique Borrione

Proceedings of the Formal Methods in Computer-Aided Design, 5th International Conference, 2004

Combining Several Paradigms for Circuit Validation and Verification.

Diana Toma, Dominique Borrione, Ghiath Al Sammane

Proceedings of the Construction and Analysis of Safe, 2004

2003

Validation of asynchronous circuit specifications using IF/CADP.

Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani

Proceedings of the IFIP VLSI-SoC 2003, 2003

Symbolic Simulation as a Simplifying Strategy for SoC Verification.

Emil Dumitrescu, Dominique Borrione

Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow.

Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Siriani

Proceedings of the 36th Hawaii International Conference on System Sciences (HICSS-36 2003), 2003

Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications.

Dominique Borrione, Menouer Boubekeur

Proceedings of the Forum on specification and Design Languages, 2003

Constrained Symbolic Simulation with Mathematica and ACL2.

Ghiath Al Sammane, Diana Toma, Julien Schmaltz, Pierre Ostier, Dominique Borrione

Proceedings of the Correct Hardware Design and Verification Methods, 2003

2002

Improving Static Ordering of BDDs for Reachability Analysis.

Jorgiano Vidal, David Déharbe, Dominique Borrione

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Formal Verification Techniques: Industrial Status and Perspectives.

Joel Blasquez, Marten van Hulst, Andrea Fedeli, Jean-Luc Lambert, Dominique Borrione, Coby Hanoch, Pierre Bricaud

Proceedings of the 2002 Design, 2002

2001

On the use of don't cares during symbolic reachability analysis.

Sherief Reda, Ayman Wahba, Ashraf Salem, Dominique Borrione, M. Ghonaimy

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

A compositional model for the functional verification of high-level synthesis results.

Dominique Borrione, Julia Dushina, Laurence V. Pierre

IEEE Trans. Very Large Scale Integr. Syst., 2000

Using the ACL2 Theorem Prover to Reason about VHDL Components.

Vanderlei Moraes Rodrigues, Dominique Borrione, Philippe Georgelin

RITA, 2000

An ACL2 Model of VHDL for Symbolic Simulation and Formal Verification.

Vanderlei Moraes Rodrigues, Dominique Borrione, Philippe Georgelin

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

1999

Design Error Diagnosis in Digital Circuits without Error Model.

Raimund Ubar, Dominique Borrione

Proceedings of the VLSI: Systems on a Chip, 1999

1998

Generation of Tests for the Localization of Single Gate Design Errors in Combinational Circuits using the Stuck-at Fault Model.

Raimund Ubar, Dominique Borrione

Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

Formalization of Finite State Machines with Data Path for the Verification of High-Level Synthesis.

Dominique Borrione, Julia Dushina, Laurence Pierre

Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

1997

Connection error location and correction in combinational circuits.

Ayman M. Wahba, Dominique Borrione

Proceedings of the European Design and Test Conference, 1997

An approach to Verilog-VHDL interoperability for synchronous designs.

Dominique Borrione, F. Vestman, H. Bouamama

Proceedings of the Advances in Hardware Design and Verification, 1997

1996

A method for automatic design error location and correction in combinational logic circuits.

Ayman M. Wahba, Dominique Borrione

J. Electron. Test., 1996

HDL-Based Integration of Formal Methods and CAD Tools in the PREVAIL Environment.

Dominique Borrione, H. Bouamama, David Déharbe, C. Le Faou, Ayman M. Wahba

Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996

Automatic diagnosis may replace simulation for correcting simple design errors.

Ayman M. Wahba, Dominique Borrione

Proceedings of the conference on European design automation, 1996

1995

Denotational Semantics of a Synchronous VHDL Subset.

Dominique Borrione, Ashraf M. Salem

Formal Methods Syst. Des., 1995

Design error diagnosis in sequential circuits.

Ayman M. Wahba, Dominique Borrione

Proceedings of the Correct Hardware Design and Verification Methods, 1995

Semantics of a verification-oriented subset of VHDL.

David Déharbe, Dominique Borrione

Proceedings of the Correct Hardware Design and Verification Methods, 1995

1994

A process algebra interpretation of a verification oriented overlanguage of VHDL.

Catherine Bayol, Bernard Soulas, Dominique Borrione, Fulvio Corno, Paolo Prinetto

Proceedings of the Proceedings EURO-DAC'94, 1994

1992

Formal Verification of VHDL Descriptions in the Prevail Environment.

Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem

IEEE Des. Test Comput., 1992

Three Decades of HDLs: Part II, Conlan Through Verilog.

Dominique Borrione, Robert Piloty, Dwight D. Hill, Karl J. Lieberherr, Philip Moorby

IEEE Des. Test Comput., 1992

1989

Zero-Defect Designs, Why and How: Formal Verification vs. Automated Synthesis.

Dominique Borrione, Paolo Prinetto

Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989

1988

A functional approach to formal hardware verification: the MTI experience.

Dominique Borrione, Paolo Camurati, J. L. Paillet, Paolo Prinetto

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

1983

CONLAN Report

Robert Piloty, Dominique Borrione, Mario Barbacci, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly

Lecture Notes in Computer Science 151, Springer, ISBN: 3-540-12275-3, 1983

1982

The conlan project: Status and future plans.

Robert Piloty, Dominique Borrione

Proceedings of the 19th Design Automation Conference, 1982

1981

Langages de description de systèmes logiques : propositions pour une méthode formelle de définition.

Dominique Borrione

, 1981

1980

An Overview of CONLAN: A Formal Construction Method for Hardware Description Language.

Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly

Proceedings of the Information Processing, Proceedings of the 8th IFIP Congress 1980, Tokyo, Japan - October 6-9, 1980 and Melbourne, Australia, 1980

CONLAN: a formal construction method for hardware description languages: language application.

Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly

Proceedings of the American Federation of Information Processing Societies: 1980 National Computer Conference, 1980

CONLAN: a formal construction method for hardware description languages: language derivation.

Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly

Proceedings of the American Federation of Information Processing Societies: 1980 National Computer Conference, 1980

CONLAN: a formal construction method for hardware description languages: basic principles.

Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly

Proceedings of the American Federation of Information Processing Societies: 1980 National Computer Conference, 1980

1976

LASCAR : un langage pour la simulation et l'évaluation des architectures d'ordinateurs.

Dominique Borrione

PhD thesis, 1976