Enric Musoll

According to our database, Enric Musoll authored at least 20 papers between 1995 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

Variable-size mosaics: A process-variation aware technique to increase the performance of tile-based, massive multi-core processors.

Enric Musoll

Comput. Electr. Eng., 2011

2010

A cost-effective load-balancing policy for tile-based, massive multi-core packet processors.

Enric Musoll

ACM Trans. Embed. Comput. Syst., 2010

Hardware-Based Load Balancing for Massive Multicore Architectures Implementing Power Gating.

Enric Musoll

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Load balancing packets on a tile-based massive multi-core processor with S-NUCA.

Enric Musoll

Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2010

2009

Leakage-saving opportunities in mesh-based massive multi-core architectures.

Enric Musoll

SIGARCH Comput. Archit. News, 2009

Mesh-based many-core performance under process variations: a core yield perspective.

Enric Musoll

SIGARCH Comput. Archit. News, 2009

A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors.

Enric Musoll

IEEE Comput. Archit. Lett., 2009

Trading off higher execution latency for increased reliability in tile-based massive multi-core architectures.

Enric Musoll

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

Power Gating Clustered Many-Core Architectures.

Enric Musoll

J. Low Power Electron., 2008

Energy and thermal tradeoffs in hardware-based load balancing for clustered multi-core architectures implementing power gating.

Enric Musoll

Proceedings of the IEEE Symposium on Application Specific Processors, 2008

A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors.

Enric Musoll

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2003

Speculating to reduce unnecessary power consumption.

Enric Musoll

ACM Trans. Embed. Comput. Syst., 2003

1999

Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors.

Enric Musoll

Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

1998

Working-zone encoding for reducing the energy in microprocessor address buses.

Enric Musoll, Tomás Lang, Jordi Cortadella

IEEE Trans. Very Large Scale Integr. Syst., 1998

Register-Transfer Level Transformations for Low-Power Data-Paths.

Enric Musoll, Jordi Cortadella

Integr. Comput. Aided Eng., 1998

Extension of the working-zone-encoding method to reduce the energy on the microprocessor data bus.

Tomás Lang, Enric Musoll, Jordi Cortadella

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997

Exploiting the locality of memory references to reduce the address bus energy.

Enric Musoll, Tomás Lang, Jordi Cortadella

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

1996

Optimizing CMOS Circuits for Low Power Using Transistor Reordering.

Enric Musoll, Jordi Cortadella

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Scheduling and resource binding for low power.

Enric Musoll, Jordi Cortadella

Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

High-level synthesis techniques for reducing the activity of functional units.

Enric Musoll, Jordi Cortadella

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995