Eun-Je Park

According to our database1, Eun-Je Park authored at least 4 papers between 2019 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Implementation of an On-Chip Learning Neural Network IC Using Highly Linear Charge Trap Device.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020
A High Efficiency Variable Stage and Frequency Charge Pump for Wide Range ISPP.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A 35x10 Charge-Trap Synaptic Memory for 57xMatrix Recognition.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019
A 16x16 Programmable Anlaog Vector Matrix Multiplier using CMOS compatible Floating gate device.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019


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