Kee-Won Kwon

Orcid: 0000-0003-4513-8532

According to our database1, Kee-Won Kwon authored at least 44 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2023
Fast and Efficient Offset Compensation by Noise-Aware Pre-Charge and Operation of DRAM Bit Line Sense Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023

2022
A 6.23-bit FG-based Neuromorphic Synaptic Device with Extended Input Range by Linearity Improvement.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022

Dynamic Power Reduction of TCAM Using Selective Precharging of Match Lines.
Proceedings of the IEEE International Conference on Big Data, 2022

2021
Implementation of an On-Chip Learning Neural Network IC Using Highly Linear Charge Trap Device.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

High Linearity Vector Matrix Multiplier using Bootstrapping and Pre-Emphasis Charging of Non-linear Charge-Trap Synaptic Devices.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Binary/Ternary Vector Matrix Multiplier with 3T-2R CBRAM Cell.
Proceedings of the 18th International SoC Design Conference, 2021

A Non-linear Input Converter Inversely Pre-distorted Against Nonlinear Behavior of FG-based Neuromorphic Synaptic Devices.
Proceedings of the 18th International SoC Design Conference, 2021

2020
A 4-GHz Sub-Harmonically Injection-Locked Phase-Locked Loop With Self-Calibrated Injection Timing and Pulsewidth.
IEEE J. Solid State Circuits, 2020

Smart Adaptive Refresh for Optimum Refresh Interval Tracking using in-DRAM ECC.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A High Efficiency Variable Stage and Frequency Charge Pump for Wide Range ISPP.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

A 35x10 Charge-Trap Synaptic Memory for 57xMatrix Recognition.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019
A Study of Read Margin Enhancement for 3T2R Nonvolatile TCAM Using Adaptive Bias Training.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Power Efficient and Reliable Nonvolatile TCAM With Hi-PFO and Semi-Complementary Driver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

CMOS-Compatible Learning Device for Neuromorphic Synapse Application using Adjustable Hot Carrier Injections.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A 16x16 Programmable Anlaog Vector Matrix Multiplier using CMOS compatible Floating gate device.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019

High performance 4T-2R Non-Volatile TCAM with NMOS Booster.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019

Low Power 3T-2R Non-Volatile TCAM Cell with Dual Match-line.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019

A 4-GHz Sub-harmonically Injection-Locked Phase-Locked Loop with Self-Calibrated Injection Timing and Pulsewidth.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
Low Power Search Engine using Non-volatile Memory based TCAM with Priority Encoding and Selective Activation of Search Line and Match Line.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A Fast and Reliable Cross-Point Three-State/Cell ReRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Local NOR and global NAND match-line architecture for high performance CAM.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016
Full chip integration of 3-d cross-point ReRAM with leakage-compensating write driver and disturbance-aware sense amplifier.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
CMOS Charge Pump With No Reversion Loss and Enhanced Drivability.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A 5.2-Gb/s Low-Swing Voltage-Mode Transmitter With an AC-/DC-Coupled Equalizer and a Voltage Offset Generator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A 6.4-Gb/s Voltage-Mode Near-Ground Receiver With a One-Tap Data and Edge DFE.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A 5-Gbit/s CDR circuit with 1.4 mW multi-PFD phase rotating PLL.
IEICE Electron. Express, 2014

A 12.5-Gb/s near-GND transceiver for wire-line UHD video interfaces.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Power-Efficient Fast Write and Hidden Refresh of ReRAM Using an ADC-Based Sense Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

An all-digital PLL with supply insensitive digitally controlled oscillator.
IEICE Electron. Express, 2013

A fully digital clock and data recovery with fast frequency offset acquisition technique for MIPI LLI applications.
IEICE Electron. Express, 2013

A tracked oversampling digital data recovery for Low Latency, fast acquisition, and high jitter tolerance.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2012
A Dual Charge Pump for Quiescent Touch Sensor Power Supply.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

0.37mW/Gb/s low power SLVS transmitter for battery powered applications.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A low-power two-line inversion method for driving LCD panels.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A low-power dual-PFD phase-rotating PLL with a PFD controller for 5Gb/s serial links.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A 3.0 Gb/s clock data recovery circuits based on digital DLL for clock-embedded display interface.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A study on accelerated built-in self test of multi-Gb/s high speed interfaces.
Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2011

2010
A Power-Efficient Voltage Upconverter for Embedded EEPROM Application.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A low power CMOS compatible embedded EEPROM for passive RFID tag.
Microelectron. J., 2010

2006
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2004
Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMs.
IEEE J. Solid State Circuits, 2004


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