F. Gail Gray

Affiliations:
  • Virginia Tech, Blacksburg, VA, USA


According to our database1, F. Gail Gray authored at least 21 papers between 1971 and 2002.

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Bibliography

2002
A Multi-Language Goal-Tree Based Functional Test Planning System.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

1999
VHDL modeling and model testing for DSP applications.
IEEE Trans. Ind. Electron., 1999

1998
A goal tree based high-level test planning system for DSP real number models.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1996
Efficient approaches to testing VHDL DSP models.
J. VLSI Signal Process., 1996

1994
Reconfiguring fault-tolerant two-dimensional array architectures.
IEEE Micro, 1994

1988
Micro-operation Perturbations in Chip Level Fault Modeling.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1985
Parallel Computer Architectures and Problem Solving Strategies for the Consistent Labeling Problem.
IEEE Trans. Computers, 1985

1984
A Fault-Tolerant One-Dimensional Cellular Structure.
Proceedings of the 4th International Conference on Distributed Computing Systems, 1984

1983
Efficient Graph Automorphism by Vertex Partitioning.
Artif. Intell., 1983

1982
A simulation model of a multi-computer system solving a combinatorial problem.
Proceedings of the 14th conference on Winter Simulation, 1982

Significance of problem solving parameters on the performance of combinatorial algorithms on multi-computer parallel architectures.
Proceedings of the International Conference on Parallel Processing, 1982

1981
Self-Diagnosing Cellular Implementations of Finite-State Machines.
IEEE Trans. Computers, 1981

Tree Structured Sequential Multiple-Valued Logic Design from Universal Modules.
IEEE Trans. Computers, 1981

Fault Diagnosos in a Boolean <i>n</i> Cube Array of Microprocessors.
IEEE Trans. Computers, 1981

1979
Diagnosis of Faults in Modular Trees.
IEEE Trans. Computers, 1979

1978
Universal Modular Trees: A Design Procedure.
IEEE Trans. Computers, 1978

Fault Detection in Bilateral Arrays of Combinational Cells.
IEEE Trans. Computers, 1978

1976
Algebraic Properties of Functions Affecting Optimum Fault-Tolerant Realizations.
IEEE Trans. Computers, 1976

1975
Multiple Fault Detection in Arrays of Combinational Cells.
IEEE Trans. Computers, 1975

1974
Reconfiguration for Repair in a Class of Universal Logic Modules.
IEEE Trans. Computers, 1974

1971
Locatability of Faults in Combinational Networks.
IEEE Trans. Computers, 1971


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