Fernando Chierchie

According to our database, Fernando Chierchie authored at least 17 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

A Distortion-Free All-Digital Transmitter Based on Noise-Shaped PWM.

Juan Ignacio Morales, Fernando Chierchie, Pablo Sergio Mandolesi, Eduardo E. Paolini

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

A Digital CCD Noise Reduction Technique Experimentally Tested on a Large Batch of Scientific Sensors.

Agustín Javier Lapi, Claudio Rodrigo Chavez Blanco, Fernando Chierchie, Guillermo Fernandez Moroni, Eduardo Emilio Paolini, Juan Estrada, Javier Tiffenberg

IEEE Trans. Instrum. Meas., 2023

2022

Low Power 18-Bit PWM With 41 ps Resolution in 130-nm CMOS.

Juan Ignacio Morales, Fernando Chierchie, Pablo Sergio Mandolesi, Eduardo E. Paolini

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Multiplexed Readout for an Experiment with a Large Number of Channels Using Single-Electron Sensitivity Skipper-CCDs.

Claudio R. Chavez, Fernando Chierchie, Miguel Sofo Haro, José Lipovetzky, Guillermo Fernandez Moroni, Juan Estrada

Sensors, 2022

2021

Symbol-Rate Baseband Signal Model for RF Pulse-Width Modulation Transmitters.

Gustavo J. González, Fernando Chierchie, Fernando H. Gregorio, Eduardo E. Paolini, Juan E. Cousseau

IEEE Trans. Veh. Technol., 2021

2020

Interleaved Readout of Charge-Coupled Devices (CCDs) for Correlated Noise Reduction.

Guillermo Fernandez Moroni, Fernando Chierchie, Leandro Stefanazzi, Eduardo Emilio Paolini, Miguel Sofo Haro, Gustavo Cancelo, Javier Tiffenberg, Juan Estrada

IEEE Trans. Instrum. Meas., 2020

Baseband Model for Uniformly Sampled RF-PWM.

Fernando Chierchie, Gustavo J. González, Juan Ignacio Morales, Eduardo E. Paolini, Juan E. Cousseau, Pablo Sergio Mandolesi

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A high-resolution all-digital pulse-width modulator architecture with a tunable delay element in CMOS.

Juan Ignacio Morales, Fernando Chierchie, Pablo Sergio Mandolesi, Eduardo Emilio Paolini

Int. J. Circuit Theory Appl., 2020

Detailed modeling of the video signal and optimal readout of charge-coupled devices.

Fernando Chierchie, Guillermo Fernandez Moroni, Pedro Querejeta Simbeni, Leandro Stefanazzi, Eduardo E. Paolini, Miguel Sofo Haro, Gustavo Cancelo, Juan Estrada

Int. J. Circuit Theory Appl., 2020

2019

Table-based PWM for all-digital RF transmitters.

Juan Ignacio Morales, Fernando Chierchie, Pablo Sergio Mandolesi, Eduardo Emilio Paolini

Int. J. Circuit Theory Appl., 2019

2018

Digital Distortion-Free PWM and Click Modulation.

Fernando Chierchie, Eduardo E. Paolini

IEEE Trans. Circuits Syst. II Express Briefs, 2018

2016

Mitigation of pulse-width-modulation distortion using a digital predistorter based on memory polynomials.

Fernando Chierchie, Juan E. Cousseau, Eduardo E. Paolini, Stefan Werner

Signal Process., 2016

2015

Volterra Models for Digital PWM and Their Inverses.

Fernando Chierchie, Sven Ole Aase

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014

Low Distortion Switching Amplifier With Discrete-Time Click Modulation.

Leandro Stefanazzi, Fernando Chierchie, Eduardo E. Paolini, Alejandro R. Oliva

IEEE Trans. Ind. Electron., 2014

Simple Real-Time Digital PWM Implementation for Class-D Amplifiers With Distortion-Free Baseband.

Fernando Chierchie, Eduardo E. Paolini, Leandro Stefanazzi, Alejandro R. Oliva

IEEE Trans. Ind. Electron., 2014

2013

Real-Time Digital PWM With Zero Baseband Distortion and Low Switching Frequency.

Fernando Chierchie, Eduardo E. Paolini

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2011

Quasi-analytical spectrum of PWM signals with dead-time for multiple sinusoidal input.

Fernando Chierchie, Eduardo E. Paolini

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011