Francisco Aznar

Orcid: 0000-0003-3629-0540

According to our database1, Francisco Aznar authored at least 22 papers between 2008 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Design-Window Methodology for Inductorless Noise-Cancelling CMOS LNAs.
IEEE Access, 2022

Modeling frequency response of gm-boosted inductorless Common-Gate LNA.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

2021
A Strategy to Achieve Competitive Performance in Basic RF LNAs.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

2020
A New Approach to the Design of CMOS Inductorless Common-gate Low-noise Amplifiers.
Proceedings of the European Conference on Circuit Theory and Design, 2020

2019
Methodology for Performance Optimization in Noise- and Distortion-Canceling LNA.
Proceedings of the 16th International Conference on Synthesis, 2019

2018
Analysis of mismatch impact on image rejection ratio for passive polyphase filters.
Int. J. Circuit Theory Appl., 2018

Analysis of the Influence of Component Mismatch on Integrated Passive Polyphase Filters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Design of a low-power quadrature LC-VCO in 65 nm CMOS.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

Impact of non-idealities on passive polyphase filter performance.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2014
1-V continuous-time equalizers for multi-gigabit short-haul optical fiber communications.
Int. J. Circuit Theory Appl., 2014

2013
Multi-gigabit analog equalizers for plastic opticalfibers.
Microelectron. J., 2013

Low-voltage low-power CMOS receiver front-end for gigabit short-reach optical communications.
Int. J. Circuit Theory Appl., 2013

2012
A 1-V CMOS receiver front-end for high-speed SI-POF links.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A 0.18 μm CMOS ring VCO for clock and data recovery applications.
Microelectron. Reliab., 2011

A 0.18 μm CMOS linear-in-dB AGC post-amplifier for optical communications.
Microelectron. Reliab., 2011

A 0.18 μm CMOS transimpedance amplifier with 26 dB dynamic range at 2.5 Gb/s.
Microelectron. J., 2011

A 3.125 GHz four stage voltage controlled ring oscillator in 0.18 CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A CMOS continuous-time equalizer for short-reach optical communications.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
A 0.18-µm CMOS 1.25-Gbps front-end receiver for low-cost short reach optical communications.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
10GBase-LX4 Limiting Amplifier in 0.18 µm CMOS Digital Process with Tunable Shunt-peaking.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Highly Sensitive 2.5 Gb/s Transimpedance Amplifier in CMOS Technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Low-Voltage Linearly Tunable CMOS Transconductor With Common-Mode Feedforward.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008


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