Frank Lee

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Bibliography

2023
The Vulnerabilities Less Exploited: Cyberattacks on End-of-Life Satellites.
Proceedings of the 1st Workshop on Security of Space and Satellite Systems, SpaceSec 2023, 2023

2022
Value creation in blockchain-driven supply chain finance.
Inf. Manag., 2022

Homophily and peer-consumer behaviour in a peer-to-peer accommodation sharing economy platform.
Behav. Inf. Technol., 2022

2020
A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing.
IEEE J. Solid State Circuits, 2020

Improving the Quality of Web Harvests Using Web Curator Tool.
Proceedings of the 2020 Web Archiving & Digital Libraries Workshop (WADL 2020), 2020

2019
Unveiling the interplay between blockchain and loyalty program participation: A qualitative approach based on Bubichain.
Int. J. Inf. Manag., 2019

A 7nm 4GHz Arm<sup>®</sup>-core-based CoWoS<sup>®</sup> Chiplet Design for High Performance Computing.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Advanced Reliability-Aware Verification for Robust Circuit Design.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Cross-Cultural Analysis of Data Breach and Forgiveness.
Proceedings of the 25th Americas Conference on Information Systems, 2019

2015
Large-scale machine learning based on functional networks for biomedical big data with high performance computing platforms.
J. Comput. Sci., 2015

Efficient observation-point insertion for diagnosability enhancement in digital circuits.
Proceedings of the 2015 IEEE International Test Conference, 2015

Topological symbolic simplification for analog design.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoS<sup>TM</sup>/3D ICs.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

2013
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study.
Proceedings of the 2013 IEEE International Test Conference, 2013

3DIC from concept to reality.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
An accurate MOSFET aging model for 28 nm integrated circuit simulation.
Microelectron. Reliab., 2012

Symbolic time-varying root-locus analysis for oscillator design.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

A size sensitivity method for interactive MOS circuit sizing.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks.
Proceedings of the 2012 IEEE International Test Conference, 2012

2011
An accurate and scalable MOSFET aging model for circuit simulation.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2007
A New Flexible Algorithm for Random Yield Improvement.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

1999
Using constructors and subclasses in java and C++.
Proceedings of the Computers and Their Applications (CATA-99), 1999

1988
Chipnet: An Optical Network of Terminal and Workstations.
Comput. Networks, 1988

1987
Structural analysis of the mouse chromosomal gene encoding interleukin 4 which expresses B cell, T cell and mast cell stimulating activities.
Nucleic Acids Res., 1987

1985
An Optical Local Area Network.
Proceedings of the Kommunikation in Verteilten Systemen I, 1985


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