Takashi Yokota

Orcid: 0000-0002-3075-006X

According to our database1, Takashi Yokota authored at least 81 papers between 1986 and 2024.

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Bibliography

2024
Alchemist: A Component-Oriented Development Tool of FPGA based on Publish/Subscribe Model.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024

2023
Enhancing Cup-Stacking Method for Collective Communication.
IEICE Trans. Inf. Syst., November, 2023

2022
On a Cup-Stacking Concept in Repetitive Collective Communication.
IEICE Trans. Inf. Syst., 2022

Towards Deep Learning-Guided Multiuser SNR and Doppler Shift Detection for Next-Generation Wireless Systems.
Proceedings of the 95th IEEE Vehicular Technology Conference, 2022

Assembly code translation from ARM64 to RISC-V.
Proceedings of the 23rd ACIS International Summer Virtual Conference on Software Engineering, 2022

Comparison of reinforcement learning in game AI.
Proceedings of the 23rd ACIS International Summer Virtual Conference on Software Engineering, 2022

2021
Investigation of Input Signal Representation to CNN for Improving SNR Classification Accuracy.
Proceedings of the 94th IEEE Vehicular Technology Conference, 2021

Development of RISC-V Based Soft-core Processor with Scalable Vector Extension for Embedded System.
Proceedings of the ACIT 2021: The 8th International Virtual Conference on Applied Computing & Information Technology, Kanazawa, Japan, June 20, 2021

2020
Genetic Node-Mapping Methods for Rapid Collective Communications.
IEICE Trans. Inf. Syst., 2020

Development of Soft-Core Processor with Efficient Array Data Transfer Mechanism.
Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

Reduction of Speech Data Posteriorgrams by Compressing Maximum-likelihood State Sequences in Query by Example.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2020

2019
Accelerating Large-Scale Interconnection Network Simulation by Cellular Automata Concept.
IEICE Trans. Inf. Syst., 2019

Automatic Generation Tool of FPGA Components for Robots.
IEICE Trans. Inf. Syst., 2019

Fast Computation with Efficient Object Data Distribution for Large-Scale Hologram Generation on a Multi-GPU Cluster.
IEICE Trans. Inf. Syst., 2019

Directive-Based Parallelization of For-Loops at LLVM IR Level.
Proceedings of the 20th IEEE/ACIS International Conference on Software Engineering, 2019

High level synthesis of ROS protocol interpretation and communication circuit for FPGA.
Proceedings of the 2nd International Workshop on Robotics Software Engineering, 2019

Proposal of Scalable Vector Extension for Embedded RISC-V Soft-Core Processor.
Proceedings of the Seventh International Symposium on Computing and Networking Workshops, 2019

Realization and Preliminary Evaluation of MPI Runtime Environment on Android Cluster.
Proceedings of the Advanced Information Networking and Applications, 2019

2018
A Genetic Approach for Accelerating Communication Performance by Node Mapping.
IEICE Trans. Inf. Syst., 2018

FPGA Components for Integrating FPGAs into Robot Systems.
IEICE Trans. Inf. Syst., 2018

Overcoming the difficulty of large-scale CGH generation on multi-GPU cluster.
Proceedings of the 11th Workshop on General Purpose Processing using GPUs, 2018

Data Distribution Method for Fast Giga-scale Hologram Generation on a Multi-GPU Cluster.
Proceedings of the 2018 Workshop on Advanced Tools, 2018

Monocular color-IR imaging system applicable for various light environments.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

An Implementation of LLVM Pass for Loop Parallelization Based on IR-Level Directives.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

Development of a Robot Car by Single Line Search Method for White Line Detection with FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2018

2017
Performance of Android Cluster System Allowing Dynamic Node Reconfiguration.
Wirel. Pers. Commun., 2017

A Static Packet Scheduling Approach for Fast Collective Communication by Using PSO.
IEICE Trans. Inf. Syst., 2017

Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

Image Denoising Based on Human Visual Characteristics.
Proceedings of the International Conference on Advances in Image Processing, 2017

Large-Scale Interconnection Network Simulation Methods Based on Cellular Automata.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

Acceleration of Large-Scale CGH Generation Using Multi-GPU Cluster.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

A Translation Method of ARM Machine Code to LLVM-IR for Binary Code Parallelization and Optimization.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

Acceleration of Publish/Subscribe Messaging in ROS-compliant FPGA Component.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

2016
Enhancing Entropy Throttling: New Classes of Injection Control in Interconnection Networks.
IEICE Trans. Inf. Syst., 2016

Architecture exploration of intelligent robot system using ros-compliant FPGA component.
Proceedings of the 2016 International Symposium on Rapid System Prototyping, 2016

cReComp: Automated Design Tool for ROS-Compliant FPGA Component.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Introducing PSO for Optimal Packet Scheduling of Collective Communication.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

2015
Relaxing Heavy Congestion by State Propagation.
J. Inf. Process., 2015

Proposal of ROS-compliant FPGA Component for Low-Power Robotic Systems.
CoRR, 2015

Empirical performance study of speculative parallel processing on commercial multi-core CPU with hardware transactional memory.
Proceedings of the 2nd International Workshop on Software Engineering for Parallel Systems, 2015

An Android cluster system capable of dynamic node reconfiguration.
Proceedings of the Seventh International Conference on Ubiquitous and Future Networks, 2015

Entropy Throttling: Towards Global Congestion Control of Interconnection Networks.
Proceedings of the Third International Symposium on Computing and Networking, 2015

Performance Improvement of Large-Scale Interconnection Network Simulator by Using GPU.
Proceedings of the Third International Symposium on Computing and Networking, 2015

Efficient Translation and Execution Method for Automated Parallel Processing System by Using Valgrind.
Proceedings of the Third International Symposium on Computing and Networking, 2015

Proposal of Highly Efficient Memory Access Method Using Locked-Cache on Soft-Core Processor with SIMD Operations.
Proceedings of the Third International Symposium on Computing and Networking, 2015

2013
Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application.
SIGARCH Comput. Archit. News, 2013

An automatic thread decomposition approach for pipelined multithreading.
Int. J. High Perform. Comput. Netw., 2013

A Cellular Automata Approach for Large-Scale Interconnection Network Simulation.
Proceedings of the First International Symposium on Computing and Networking, 2013

Efficient Data Communication Using Dynamic Switching of Compression Method.
Proceedings of the First International Symposium on Computing and Networking, 2013

Exploration of Highly Accurate Path Prediction Mechanism Using Detailed Path History.
Proceedings of the First International Symposium on Computing and Networking, 2013

Runtime Overhead Reduction in Automated Parallel Processing System Using Valgrind.
Proceedings of the First International Symposium on Computing and Networking, 2013

A prototyping system for hardware distributed objects with diversity of programming languages design and preliminary evaluation.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2012
Proposal of Incremental Software Simulation for Reduction of Evaluation Time.
Proceedings of the Third International Conference on Networking and Computing, 2012

Comparative Study of Path Prediction Method for Speculative Loop Execution.
Proceedings of the Third International Conference on Networking and Computing, 2012

2011
Steady/Unsteady Communication Performance in Large-Scale Regular Networks.
Proceedings of the 25th IEEE International Conference on Advanced Information Networking and Applications Workshops, 2011

2010
Automatic Thread Decomposition for Pipelined Multithreading.
Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010

Loop Performance Improvement for Min-cut Program Decomposition Method.
Proceedings of the First International Conference on Networking and Computing, 2010

2009
Clustered Software Queue for Efficient Pipelined Multithreading.
Proceedings of the 2009 International Conference on Parallel and Distributed Computing, 2009

An Effective Throttling Method Based on Quasi-global Congestion Information.
Proceedings of the 10th International Symposium on Pervasive Systems, 2009

2008
Are Uniform Nerworks Scalable?
Proceedings of the Ninth International Conference on Parallel and Distributed Computing, 2008

Clustered Decoupled Software Pipelining on Commodity CMP.
Proceedings of the 14th International Conference on Parallel and Distributed Systems, 2008

Potentials of Branch Predictors: From Entropy Viewpoints.
Proceedings of the Architecture of Computing Systems, 2008

2007
Quasi-global routing for fault-tolerant high-performance interconnection networks.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2007

A thread partitioning technique for multithreaded execution along hot paths.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2007

Introducing entropies for representing program behavior and branch predictor performance.
Proceedings of the Workshop on Experimental Computer Science, 2007

2006
Entropy Throttling: A Physical Approach for Maximizing Packet Mobility in Interconnection Networks.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005
Design and Implementation of a VLIW Processor Simulation Environment with Instruction Scheduling Framework.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2005

Two-Path Limited Speculation Method for Static/Dynamic Optimization in Multithreaded Systems.
Proceedings of the Sixth International Conference on Parallel and Distributed Computing, 2005

Cross-Line - A Globally Adaptive Control Method of Interconnection Network.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005

2003
Receiving message prediction method.
Parallel Comput., 2003

2002
A Methodology of Binary-level Multithreading and Its Preliminary Evaluation.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002

Real-Time Medical Diagnosis on a Multiple FPGA-based System.
Proceedings of the Field-Programmable Logic and Applications, 2002

A Scalable FPGA-Based Custom Computing Machine for a Medical Image Processing.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

1997
Virtual control channel and its application to the massively parallel computer RWC-1.
Proceedings of the Fourth International on High-Performance Computing, 1997

1996
Multithread execution mechanisms on RICA-1 for massively parallel computation.
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996

1995
Reduced Interprocessor-Communication Architecture and its Implementation on EM-4.
Parallel Comput., 1995

Time Space Sharing Scheduling and Architectural Support.
Proceedings of the Job Scheduling Strategies for Parallel Processing, 1995

A prototype router for the massively parallel computer RWC-1.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1993
RICA: Reduced Interprocessor-Communication Architecture - Concept and Mechanisms.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

1987
Structural analysis of the mouse chromosomal gene encoding interleukin 4 which expresses B cell, T cell and mast cell stimulating activities.
Nucleic Acids Res., 1987

1986
Dynamic fault recovery in mesh-connected parallel computers.
Syst. Comput. Jpn., 1986


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