Gabriel A. G. Andrade

Orcid: 0000-0003-2269-7331

According to our database1, Gabriel A. G. Andrade authored at least 8 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
EveCheck: An Event-Driven, Scalable Algorithm for Coherent Shared Memory Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

2020
Chaining and Biasing: Test Generation Techniques for Shared-Memory Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Directed Test Generator for Shared-Memory Verification of Multicore Chip Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Reinforcement Learning Approach to Directed Test Generation for Shared Memory Verification.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2018
Steep coverage-ascent directed test generation for shared-memory verification of multicore chips.
Proceedings of the International Conference on Computer-Aided Design, 2018

2016
Chain-based pseudorandom tests for pre-silicon verification of CMP memory systems.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2012
A template for the construction of efficient checkers with full verification guarantees.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Efficient verification of out-of-order behaviors with relaxed scoreboards.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012


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