Marleson Graf

Orcid: 0000-0003-3636-1126

According to our database1, Marleson Graf authored at least 6 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
EveCheck: An Event-Driven, Scalable Algorithm for Coherent Shared Memory Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

2020
Chaining and Biasing: Test Generation Techniques for Shared-Memory Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Directed Test Generator for Shared-Memory Verification of Multicore Chip Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
Spec&Check: An Approach to the Building of Shared-Memory Runtime Checkers for Multicore Chip Design Verification.
Proceedings of the International Conference on Computer-Aided Design, 2019

2018
Steep coverage-ascent directed test generation for shared-memory verification of multicore chips.
Proceedings of the International Conference on Computer-Aided Design, 2018

2016
Chain-based pseudorandom tests for pre-silicon verification of CMP memory systems.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016


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