Ganpat Anant Parulekar

According to our database, Ganpat Anant Parulekar authored at least 6 papers between 2020 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A modulation format and data-rate independent linear ratioed impedance and driver based true full duplex IO.

Ganpat Anant Parulekar, Sandeep Goyal, Nikhil Ajith, Ishan Mishra, Shalabh Gupta

Microelectron. J., 2026

2024

A Compact Low-Power 29 Gb/s Pseudo Random Quaternary Sequence Generator in 65 nm CMOS.

Ishan Mishra, Ganpat Anant Parulekar, Shalabh Gupta

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

A PAM-4 Based Full Duplex IO with In-built Feed-Forward Equalizer and Performance Enhanced Receiver.

Ganpat Anant Parulekar, Shalabh Gupta

Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

2023

A Linear Ratioed Impedance and Driver-Based True Full-Duplex IO with Background Self-Interference Cancellation.

Ganpat Anant Parulekar, Sandeep Goyal, Nikhil Ajith, Ishan Mishra, Shalabh Gupta

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022

A True Full-Duplex IO (TFD-IO) With Background SI Cancellation for High-Density Interfaces.

Sandeep Goyal, Ganpat Anant Parulekar, Shalabh Gupta

IEEE Trans. Very Large Scale Integr. Syst., 2022

2020

A True Full-Duplex IO for High-Density High-Speed Interconnects.

Sandeep Goyal, Ganpat Anant Parulekar, Shalabh Gupta

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020