Garo Bournoutian

According to our database, Garo Bournoutian authored at least 10 papers between 2008 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Mobile ecosystem driven application-specific low-power control microarchitecture.

Garo Bournoutian, Alex Orailoglu

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Mobile Ecosystem Driven Dynamic Pipeline Adaptation for Low Power.

Garo Bournoutian, Alex Orailoglu

Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

2014

Architectural and Software Optimizations for Next- Generation Heterogeneous Low-Power Mobile Application Processors /.

Garo Bournoutian

PhD thesis, 2014

On-device objective-C application optimization framework for high-performance mobile processors.

Garo Bournoutian, Alex Orailoglu

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Application-aware adaptive cache architecture for power-sensitive mobile processors.

Garo Bournoutian, Alex Orailoglu

ACM Trans. Embed. Comput. Syst., 2013

2012

Dynamic transient fault detection and recovery for embedded processor datapaths.

Garo Bournoutian, Alex Orailoglu

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011

Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors.

Garo Bournoutian, Alex Orailoglu

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010

Dynamic, non-linear cache architecture for power-sensitive mobile processors.

Garo Bournoutian, Alex Orailoglu

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009

Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions.

Garo Bournoutian, Alex Orailoglu

Proceedings of the 2009 International Conference on Compilers, 2009

2008

Miss reduction in embedded processors through dynamic, power-friendly cache design.

Garo Bournoutian, Alex Orailoglu

Proceedings of the 45th Design Automation Conference, 2008