Alex Orailoglu

Affiliations:
  • University of California, San Diego, USA


According to our database1, Alex Orailoglu authored at least 278 papers between 1983 and 2023.

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Bibliography

2023
Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

Redundancy Attack: Breaking Logic Locking Through Oracleless Rationality Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

Shaping Resilient AI Hardware Through DNN Computational Feature Exploitation.
IEEE Des. Test, April, 2023

Thwarting Reverse Engineering Attacks through Keyless Logic Obfuscation.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

ClearLock: Deterring Hardware Reverse Engineering Attacks in a White-Box.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022
Architecting Decentralization and Customizability in DNN Accelerators for Hardware Defect Adaptation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Guest Editorial: Special Issue on 2020 IEEE International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2020).
Int. J. Parallel Program., 2022

JANUS-HD: Exploiting FSM Sequentiality and Synthesis Flexibility in Logic Obfuscation to Thwart SAT Attack While Offering Strong Corruption.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction.
IEEE Trans. Very Large Scale Integr. Syst., 2021

SNR: Squeezing Numerical Range Defuses Bit Error Vulnerability Surface in Deep Neural Networks.
ACM Trans. Embed. Comput. Syst., 2021

Evolving Complementary Sparsity Patterns for Hardware-Friendly Inference of Sparse DNNs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

JANUS: Boosting Logic Obfuscation Scope Through Reconfigurable FSM Synthesis.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

2020
Boosting Bit-Error Resilience of DNN Accelerators Through Median Feature Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Low-Cost Error Detection in Deep Neural Network Accelerators with Linear Algorithmic Checksums.
J. Electron. Test., 2020

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.
CoRR, 2020

Taming Combinational Trojan Detection Challenges with Self-Referencing Adaptive Test Patterns.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Squeezing Correlated Neurons for Resource-Efficient Deep Neural Networks.
Proceedings of the Machine Learning and Knowledge Discovery in Databases, 2020

A Crowd-Based Explosive Detection System with Two-Level Feedback Sensor Calibration.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Just Say Zero: Containing Critical Bit-Error Propagation in Deep Neural Networks With Anomalous Feature Suppression.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Test Pattern Superposition to Detect Hardware Trojans.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Hunting Sybils in Participatory Mobile Consensus-Based Networks.
Proceedings of the ASIA CCS '20: The 15th ACM Asia Conference on Computer and Communications Security, 2020

Concurrent Monitoring of Operational Health in Neural Networks Through Balanced Output Partitions.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Detecting Gas Vapor Leaks Using Uncalibrated Sensors.
IEEE Access, 2019

Shielding Logic Locking from Redundancy Attacks.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Detecting Gas Vapor Leaks through Uncalibrated Sensor Based CPS.
Proceedings of the IEEE International Conference on Acoustics, 2019

Piercing Logic Locking Keys through Redundancy Identification.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Sanity-Check: Boosting the Reliability of Safety-Critical Deep Neural Network Applications.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

The Return of Power Gating: Smart Leakage Energy Reductions in Modern Out-of-Order Processor Architectures.
Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019

2018
Variation-Aware Hardware Trojan Detection through Power Side-channel.
Proceedings of the IEEE International Test Conference, 2018

2017
Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

Ensuring system security through proximity based authentication.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Aggressive Test Cost Reductions Through Continuous Test Effectiveness Assessment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Power-Aware Delay Test Quality Optimization for Multiple Frequency Domains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2015
Joint Profit and Process Variation Aware High Level Synthesis With Speed Binning.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Mobile ecosystem driven application-specific low-power control microarchitecture.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Mobile Ecosystem Driven Dynamic Pipeline Adaptation for Low Power.
Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

2014
Examining Timing Path Robustness Under Wide-Bandwidth Power Supply Noise Through Multi-Functional-Cycle Delay Test.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Branch Prediction-Directed Dynamic Instruction Cache Locking for Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2014

Sleep-aware variable partitioning for energy-efficient hybrid PRAM and DRAM main memory.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

On-device objective-C application optimization framework for high-performance mobile processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Register allocation for embedded systems to simultaneously reduce energy and temperature on registers.
ACM Trans. Embed. Comput. Syst., 2013

Application-aware adaptive cache architecture for power-sensitive mobile processors.
ACM Trans. Embed. Comput. Syst., 2013

Towards a cost-effective hardware trojan detection methodology.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Tracing the best test mix through multi-variate quality tracking.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Profit maximization through process variation aware high level synthesis with speed binning.
Proceedings of the Design, Automation and Test in Europe, 2013

Full exploitation of process variation space for continuous delivery of optimal delay test quality.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Tackling Resource Variations Through Adaptive Multicore Execution Frameworks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

On Diagnosis of Timing Failures in Scan Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Small-delay defects detection under process variation using Inter-Path Correlation.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Delay test resource allocation and scheduling for multiple frequency domains.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Dynamic transient fault detection and recovery for embedded processor datapaths.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Full Fault Resilience and Relaxed Synchronization Requirements at the Cache-Memory Interface.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Migration-aware adaptive MPSoC static schedules with dynamic reconfigurability.
J. Parallel Distributed Comput., 2011

Toward Future Systems with Nanoscale Devices: Overcoming the Reliability Challenge.
Computer, 2011

Frugal but flexible multicore topologies in support of resource variation-driven adaptivity.
Proceedings of the Design, Automation and Test in Europe, 2011

Register allocation for simultaneous reduction of energy and peak temperature on registers.
Proceedings of the Design, Automation and Test in Europe, 2011

Diagnosing scan chain timing faults through statistical feature analysis of scan images.
Proceedings of the Design, Automation and Test in Europe, 2011

Adaptive test optimization through real time learning of test effectiveness.
Proceedings of the Design, Automation and Test in Europe, 2011

Diagnosing scan clock delay faults through statistical timing pruning.
Proceedings of the 48th Design Automation Conference, 2011

Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Adaptive Test Framework for Achieving Target Test Quality at Minimal Cost.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
DiSC: A New Diagnosis Method for Multiple Scan Chain Failures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Squashing code size in microcoded IPs while delivering high decompression speed.
Des. Autom. Embed. Syst., 2010

Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions.
Des. Autom. Embed. Syst., 2010

VDDmin test optimization for overscreening minimization through adaptive scan chain masking.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Fine-grained adaptive CMP cache sharing through access history exploitation.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Fully adaptive multicore architectures through statically-directed dynamic execution reconfigurations.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Delay test quality maximization through process-aware selection of test set size.
Proceedings of the 28th International Conference on Computer Design, 2010

Performance and energy efficient cache migrationapproach for thermal management in embedded systems.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme.
Proceedings of the Design, Automation and Test in Europe, 2010

High durability in NAND flash memory through effective page reuse mechanisms.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Dynamic, non-linear cache architecture for power-sensitive mobile processors.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009
Low-Power Scan Testing for Test Data Compression Using a Routing-Driven Scan Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Guest Editorial Special Section on the IEEE Symposium on Application Specific Processors 2008.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Scan Cell Positioning for Boosting the Compression of Fan-Out Networks.
J. Comput. Sci. Technol., 2009

Logic Mapping in Crossbar-Based Nanoarchitectures.
IEEE Des. Test Comput., 2009

Scan power reduction in linear test data compression scheme.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Deflecting crosstalk by routing reconsideration through refined signal correlation estimation.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Processor reliability enhancement through compiler-directed register file peak temperature reduction.
Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009

Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude.
Proceedings of the Design, Automation and Test in Europe, 2009

Making DNA self-assembly error-proof: Attaining small growth error rates through embedded information redundancy.
Proceedings of the Design, Automation and Test in Europe, 2009

Squashing microcode stores to size in embedded systems while delivering rapid microcode accesses.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Filtering Global History: Power and Performance Efficient Branch Predictor.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008
Scheduling Power-Constrained Tests through the SoC Functional Bus.
IEICE Trans. Inf. Syst., 2008

Application Specific Low Latency Instruction Cache for NAND Flash Memory Based Embedded Systems.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008

Locality aware redundancy allocation in nanoelectronic systems.
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008

Online test and fault-tolerance for nanoelectronic programmable logic arrays.
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008

Test cost minimization through adaptive test development.
Proceedings of the 26th International Conference on Computer Design, 2008

Towards fault tolerant parallel prefix adders in nanoelectronic systems.
Proceedings of the Design, Automation and Test in Europe, 2008

Miss reduction in embedded processors through dynamic, power-friendly cache design.
Proceedings of the 45th Design Automation Conference, 2008

Application specific non-volatile primary memory for embedded systems.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization.
Proceedings of the 2008 International Conference on Compilers, 2008

2007
Guest Editorial.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

On the identification of modular test requirements for low cost hierarchical test path construction.
Integr., 2007

Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory.
Int. J. Parallel Program., 2007

Towards Nanoelectronics Processor Architectures.
J. Electron. Test., 2007

Architectures for Silicon Nanoelectronics and Beyond.
Computer, 2007

Design automation for hybrid CMOS-nonoelectronics crossbars.
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

Circuit-level mismatch modelling and yield optimization for CMOS analog circuits.
Proceedings of the 25th International Conference on Computer Design, 2007

Power efficient register file update approach for embedded processors.
Proceedings of the 25th International Conference on Computer Design, 2007

Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays.
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs.
Proceedings of the 2007 International Conference on Compilers, 2007

Improving Circuit Robustness with Cost-Effective Soft-Error-Tolerant Sequential Elements.
Proceedings of the 16th Asian Test Symposium, 2007

Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Decision Tree Based Mismatch Diagnosis in Analog Circuits.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Power-Constrained SOC Test Schedules through Utilization of Functional Buses.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics.
Proceedings of the 11th European Test Symposium, 2006

Topology aware mapping of logic functions onto nanowire-based crossbar architectures.
Proceedings of the 43rd Design Automation Conference, 2006

Power efficient branch prediction through early identification of branch addresses.
Proceedings of the 2006 International Conference on Compilers, 2006

Power-efficient instruction delivery through trace reuse.
Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005
Test power reductions through computationally efficient, decoupled scan chain modifications.
IEEE Trans. Reliab., 2005

A reprogrammable customization framework for efficient branch resolution in embedded processors.
ACM Trans. Embed. Comput. Syst., 2005

The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations.
IEEE Trans. Computers, 2005

Efficient RT-Level Fault Diagnosis.
J. Comput. Sci. Technol., 2005

Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs.
Proceedings of the 42nd Design Automation Conference, 2005

Energy-effcient physically tagged caches for embedded processors with virtual memory.
Proceedings of the 42nd Design Automation Conference, 2005

Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Forward discrete probability propagation method for device performance characterization under process variations.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Fault tolerant nanoelectronic processor architectures.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Low-power instruction bus encoding for embedded processors.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test.
IEEE Trans. Reliab., 2004

Tag compression for low power in dynamically customizable embedded processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Transforming Binary Code for Low-Power Embedded Processors.
IEEE Micro, 2004

Fast and energy-frugal deterministic test through efficient compression and compaction techniques.
J. Syst. Archit., 2004

Searching for Global Test Costs Optimization in Core-Based Systems.
J. Electron. Test., 2004

Seamless Test of Digital Components in Mixed-Signal Paths.
IEEE Des. Test Comput., 2004

Application specific instruction memory transformations for power efficient, fault resilient embedded processors.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Autonomous Yet Deterministic Test of SOC Cores.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Test Cost Reduction Through A Reconfigurable Scan Architecture.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Extending the Applicability of Parallel-Serial Scan Designs.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Frugal linear network-based test decompression for drastic test cost reductions.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Design space exploration for aggressive test cost reduction in CircularScan architectures.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Pipelined test of SOC cores through test data transformations.
Proceedings of the 9th European Test Symposium, 2004

Scan Power Minimization through Stimulus and Response Transformations.
Proceedings of the 2004 Design, 2004

CircularScan: A Scan Architecture for Test Cost Reduction.
Proceedings of the 2004 Design, 2004

On mismatch in the deep sub-micron era - from physics to circuits.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Efficient RT-level fault diagnosis methodology.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs.
IEEE Trans. Computers, 2003

Guest Editor's Introduction.
Int. J. Parallel Program., 2003

Reducing Average and Peak Test Power Through Scan Chain Modification.
J. Electron. Test., 2003

Statistical Tolerance Analysis for Assured Analog Test Coverage.
J. Electron. Test., 2003

Compacting Test Responses for Deeply Embedded SoC Cores.
IEEE Des. Test Comput., 2003

Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors.
IEEE Des. Test Comput., 2003

Guest Editors' Introduction: Application-Specific Microprocessors.
IEEE Des. Test Comput., 2003

Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Modeling Scan Chain Modifications For Scan-in Test Power Minimization.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Aggressive Test Power Reduction Through Test Stimuli Transformation.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Virtual Page Tag Reduction for Low-power TLBs.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Partial Core Encryption for Performance-Efficient Test of SOCs.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Compiler-Based Register Name Adjustment for Low-Power Embedded Processors.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Parity-based output compaction for core-based SOCs [logic testing].
Proceedings of the 8th European Test Workshop, 2003

Hierarchical Constraint Conscious RT-level Test Generation.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

Low-power Branch Target Buffer for Application-Specific Embedded Processors.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

Customizable Embedded Processor Architectures.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

Virtual Compression through Test Vector Stitching for Scan Based Designs.
Proceedings of the 2003 Design, 2003

Power Efficiency through Application-Specific Instruction Memory Transformations.
Proceedings of the 2003 Design, 2003

Test application time and volume compression through seed overlapping.
Proceedings of the 40th Design Automation Conference, 2003

Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Microarchitectural synthesis of performance-constrained, low-power VLSI designs.
ACM Trans. Design Autom. Electr. Syst., 2002

Efficient Construction of Aliasing-Free Compaction Circuitry.
IEEE Micro, 2002

Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface.
J. Electron. Test., 2002

Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers.
IEEE Des. Test Comput., 2002

Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST.
IEEE Des. Test Comput., 2002

Test Power Reduction through Minimization of Scan Chain Transitions.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Generic and Detailed Search for TAM Definition in Core-Based Systems.
Proceedings of the 3rd Latin American Test Workshop, 2002

Scan Power Reduction Through Test Data Transition Frequency Analysis.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Low-Power Data Memory Communication for Application-Specific Embedded Processors.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

On the Relation between SAT and BDDs for Equivalence Checking.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

An Integrated Tool for Analog Test Generation and Fault Simulation.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Automated test development and test time reduction for RF subsystems.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Fault Dictionary Size Reduction through Test Response Superposition.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

A novel scan architecture for power-efficient, rapid test.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Dynamic test data transformations for average and peak power reductions.
Proceedings of the 7th European Test Workshop, 2002

Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Reducing Test Application Time Through Test Data Mutation Encoding.
Proceedings of the 2002 Design, 2002

Power Efficient Embedded Processor Ip's through Application-Specific Tag Compression in Data Caches.
Proceedings of the 2002 Design, 2002

Test Planning and Design Space Exploration in a Core-Based Environment.
Proceedings of the 2002 Design, 2002

Gate Level Fault Diagnosis in Scan-Based BIST.
Proceedings of the 2002 Design, 2002

Energy frugal tags in reprogrammable I-caches for application-specific embedded processors.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

Test Requirement Analysis for Low Cost Hierarchical Test Path Construction.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Performance and power effectiveness in embedded processors customizable partitioned caches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Concurrent test for digital linear systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

RT-level Fault Simulation Based on Symbolic Propagation.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Efficient Transparency Extraction and Utilization in Hierarchical Test.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Improved Methods for Fault Diagnosis in Scan-Based BIST.
Proceedings of the 2nd Latin American Test Workshop, 2001

Space and time compaction schemes for embedded cores.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Testability implications in low-cost integrated radio transceivers: a Bluetooth case study.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Data cache energy minimizations through programmable tag size matching to the applications.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Diagnosis for scan-based BIST: reaching deep into the signatures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors.
Proceedings of the 38th Design Automation Conference, 2001

Test Volume and Application Time Reduction Through Scan Chain Concealment.
Proceedings of the 38th Design Automation Conference, 2001

Towards effective embedded processors in codesigns: customizable partitioned caches.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

Low-cost, software-based self-test methodologies for performance faults in processor control subsystems.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

Compaction Schemes with Minimum Test Application Time.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck?
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
On-line test for fault-secure fault identification.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Invariance-Based On-Line Test for RTL Controller-Datapath Circuits.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Block-Based Test Integration for Analog Integrated Circuits.
Proceedings of the 1st Latin American Test Workshop, 2000

Exploiting Off-Line Hierarchical Test Paths in Module Diagnosis and On-Line Test.
Proceedings of the 1st Latin American Test Workshop, 2000

Deterministic partitioning techniques for fault diagnosis in scan-based BIST.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Transparency-based hierarchical test generation for modular RTL designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Unifying methodologies for high fault coverage concurrent and off-line test of digital filters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Cost effective digital filter design for concurrent test.
Proceedings of the IEEE International Conference on Acoustics, 2000

How to avoid random walks in hierarchical test path identification.
Proceedings of the 5th European Test Workshop, 2000

Low cost concurrent test implementation for linear digital systems.
Proceedings of the 5th European Test Workshop, 2000

Test Synthesis for Mixed-Signal SOC Paths.
Proceedings of the 2000 Design, 2000

Test Quality and Fault Risk in Digital Filter Datapath BIST.
Proceedings of the 2000 Design, 2000

Improved fault diagnosis in scan-based BIST via superposition.
Proceedings of the 37th Conference on Design Automation, 2000

Modular test generation and concurrent transparency-based test translation using gate-level ATPG.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

Fast hierarchical test path construction for DFT-free controller-datapath circuits.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Accumulation-based concurrent fault detection for linear digital state variable systems.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
Redundancy and testability in digital filter datapaths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Low-Cost On-Line Test for Digital Filters.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Property-based testability analysis for hierarchical RTL designs.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Low-Cost Test for Large Analog IC's.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Channel-Based Behavioral Test Synthesis for Improved Module Reachability.
Proceedings of the 1999 Design, 1999

Self Recovering Controller and Datapath Codesign.
Proceedings of the 1999 Design, 1999

TRANSPARENT: a system for RTL testability analysis, DFT guidance and hierarchical test generation.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998
On-Line Fault Resilience Through Gracefully Degradable ASICs.
J. Electron. Test., 1998

RTL Test Justification and Propagation Analysis for Modular Designs.
J. Electron. Test., 1998

Efficient Self-Recovering ASIC Design.
IEEE Des. Test Comput., 1998

DFT guidance through RTL test justification and propagation analysis.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Graceful Degradation in Synthesis of VLSI ICs.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Transient and Intermittent Fault Recovery without Rollback.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs.
Proceedings of the 1998 Design, 1998

An Examination of PRPG Selection Approaches for Large, Industrial Designs.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction.
VLSI Design, 1997

Microarchitectural synthesis for rapid BIST testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Microarchitectural Synthesis of ICs with Embedded Concurrent Fault Isolation.
Proceedings of the Digest of Papers: FTCS-27, 1997

Frequency-Domain Compatibility in Digital Filter BIST.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors.
IEEE Trans. Reliab., 1996

Automatic Synthesis of Self-Recovering VLSI Systems.
IEEE Trans. Computers, 1996

Computer-Aided Design of Fault-Tolerant VLSI Systems.
IEEE Des. Test Comput., 1996

Can Defect-Tolerant Chips Better Meet the Quality Challenge?
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Variance mismatch: identifying random-test resistance in DSP datapaths.
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

High-level synthesis of gracefully degradable ASICs.
Proceedings of the 1996 European Design and Test Conference, 1996

Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Testability metrics for synthesis of self-testable designs and effective test plans.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Towards 100% Testable FIR Digital Filters.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Metric-based transformations for self testable VLSI designs with high test concurrency.
Proceedings of the Proceedings EURO-DAC'95, 1995

1994
Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures.
IEEE Trans. Very Large Scale Integr. Syst., 1994

Synthesis of fault-tolerant and real-time microarchitectures.
J. Syst. Softw., 1994

Rapid prototyping of fault-tolerant VLSI systems.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Integrating Binding Constraints in the Synthesis of Area-Efficient Self-Recovering Microarchitectures.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Simulated annealing based yield enhancement of layouts.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis.
Proceedings of the 31st Conference on Design Automation, 1994

Microarchitectural Synthesis of VLSI Designs with High Test Concurrency.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Intertwined Scheduling, Module Selection and Allocation in Time-and-Area.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Test Path Generation and Test Scheduling for Self-Testable Designs.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Optimal Self-Recovering Microarchitecture Synthesis.
Proceedings of the Digest of Papers: FTCS-23, 1993

High-Level Synthesis of Fault-Secure Microarchitectures.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
High-Level Synthesis of Self-Recovering MicroArchitectures.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs.
Proceedings of the Digest of Papers: FTCS-22, 1992

Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs.
Proceedings of the 29th Design Automation Conference, 1992

1991
Hierarchical Modeling of the VLSI Design Process.
IEEE Expert, 1991

ALPS: An Algorithm for Pipeline Data Path Synthesis.
Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

1986
Flow graph representation.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1983
Software Design Issues in the Implementation of Hierarchical, Display Editors
PhD thesis, 1983


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