Alex Orailoglu
Orcid: 0000-0002-6104-3923Affiliations:
- University of California, San Diego, USA
According to our database1,
Alex Orailoglu
authored at least 279 papers
between 1983 and 2024.
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Bibliography
2024
2023
Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
IEEE Des. Test, April, 2023
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Proceedings of the 32nd IEEE Asian Test Symposium, 2023
2022
Architecting Decentralization and Customizability in DNN Accelerators for Hardware Defect Adaptation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Guest Editorial: Special Issue on 2020 IEEE International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2020).
Int. J. Parallel Program., 2022
JANUS-HD: Exploiting FSM Sequentiality and Synthesis Flexibility in Logic Obfuscation to Thwart SAT Attack While Offering Strong Corruption.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction.
IEEE Trans. Very Large Scale Integr. Syst., 2021
SNR: Squeezing Numerical Range Defuses Bit Error Vulnerability Surface in Deep Neural Networks.
ACM Trans. Embed. Comput. Syst., 2021
Evolving Complementary Sparsity Patterns for Hardware-Friendly Inference of Sparse DNNs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Low-Cost Error Detection in Deep Neural Network Accelerators with Linear Algorithmic Checksums.
J. Electron. Test., 2020
CoRR, 2020
Taming Combinational Trojan Detection Challenges with Self-Referencing Adaptive Test Patterns.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Proceedings of the Machine Learning and Knowledge Discovery in Databases, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Just Say Zero: Containing Critical Bit-Error Propagation in Deep Neural Networks With Anomalous Feature Suppression.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the ASIA CCS '20: The 15th ACM Asia Conference on Computer and Communications Security, 2020
Concurrent Monitoring of Operational Health in Neural Networks Through Balanced Output Partitions.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Proceedings of the IEEE International Conference on Acoustics, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Sanity-Check: Boosting the Reliability of Safety-Critical Deep Neural Network Applications.
Proceedings of the 28th IEEE Asian Test Symposium, 2019
The Return of Power Gating: Smart Leakage Energy Reductions in Modern Out-of-Order Processor Architectures.
Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019
2018
Proceedings of the IEEE International Test Conference, 2018
2017
Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions.
Proceedings of the 22nd IEEE European Test Symposium, 2017
Proceedings of the 26th IEEE Asian Test Symposium, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015
2014
Examining Timing Path Robustness Under Wide-Bandwidth Power Supply Noise Through Multi-Functional-Cycle Delay Test.
IEEE Trans. Very Large Scale Integr. Syst., 2014
ACM Trans. Embed. Comput. Syst., 2014
Sleep-aware variable partitioning for energy-efficient hybrid PRAM and DRAM main memory.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
On-device objective-C application optimization framework for high-performance mobile processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Register allocation for embedded systems to simultaneously reduce energy and temperature on registers.
ACM Trans. Embed. Comput. Syst., 2013
ACM Trans. Embed. Comput. Syst., 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Profit maximization through process variation aware high level synthesis with speed binning.
Proceedings of the Design, Automation and Test in Europe, 2013
Full exploitation of process variation space for continuous delivery of optimal delay test quality.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
2011
Full Fault Resilience and Relaxed Synchronization Requirements at the Cache-Memory Interface.
IEEE Trans. Very Large Scale Integr. Syst., 2011
J. Parallel Distributed Comput., 2011
Computer, 2011
Frugal but flexible multicore topologies in support of resource variation-driven adaptivity.
Proceedings of the Design, Automation and Test in Europe, 2011
Register allocation for simultaneous reduction of energy and peak temperature on registers.
Proceedings of the Design, Automation and Test in Europe, 2011
Diagnosing scan chain timing faults through statistical feature analysis of scan images.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 48th Design Automation Conference, 2011
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Des. Autom. Embed. Syst., 2010
Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions.
Des. Autom. Embed. Syst., 2010
VDDmin test optimization for overscreening minimization through adaptive scan chain masking.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Fully adaptive multicore architectures through statically-directed dynamic execution reconfigurations.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the 28th International Conference on Computer Design, 2010
Performance and energy efficient cache migrationapproach for thermal management in embedded systems.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010
2009
Low-Power Scan Testing for Test Data Compression Using a Routing-Driven Scan Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Guest Editorial Special Section on the IEEE Symposium on Application Specific Processors 2008.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
J. Comput. Sci. Technol., 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Deflecting crosstalk by routing reconsideration through refined signal correlation estimation.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Processor reliability enhancement through compiler-directed register file peak temperature reduction.
Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude.
Proceedings of the Design, Automation and Test in Europe, 2009
Making DNA self-assembly error-proof: Attaining small growth error rates through embedded information redundancy.
Proceedings of the Design, Automation and Test in Europe, 2009
Squashing microcode stores to size in embedded systems while delivering rapid microcode accesses.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009
2008
IEICE Trans. Inf. Syst., 2008
Application Specific Low Latency Instruction Cache for NAND Flash Memory Based Embedded Systems.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008
Proceedings of the 26th International Conference on Computer Design, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008
A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization.
Proceedings of the 2008 International Conference on Compilers, 2008
2007
On the identification of modular test requirements for low cost hierarchical test path construction.
Integr., 2007
Int. J. Parallel Program., 2007
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007
Proceedings of the 25th International Conference on Computer Design, 2007
Proceedings of the 25th International Conference on Computer Design, 2007
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007
Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs.
Proceedings of the 2007 International Conference on Compilers, 2007
Improving Circuit Robustness with Cost-Effective Soft-Error-Tolerant Sequential Elements.
Proceedings of the 16th Asian Test Symposium, 2007
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics.
Proceedings of the 11th European Test Symposium, 2006
Topology aware mapping of logic functions onto nanowire-based crossbar architectures.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 2006 International Conference on Compilers, 2006
Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006
2005
Test power reductions through computationally efficient, decoupled scan chain modifications.
IEEE Trans. Reliab., 2005
A reprogrammable customization framework for efficient branch resolution in embedded processors.
ACM Trans. Embed. Comput. Syst., 2005
The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations.
IEEE Trans. Computers, 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs.
Proceedings of the 42nd Design Automation Conference, 2005
Energy-effcient physically tagged caches for embedded processors with virtual memory.
Proceedings of the 42nd Design Automation Conference, 2005
Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Forward discrete probability propagation method for device performance characterization under process variations.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead.
IEEE Trans. Very Large Scale Integr. Syst., 2004
Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test.
IEEE Trans. Reliab., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Fast and energy-frugal deterministic test through efficient compression and compaction techniques.
J. Syst. Archit., 2004
J. Electron. Test., 2004
IEEE Des. Test Comput., 2004
Application specific instruction memory transformations for power efficient, fault resilient embedded processors.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Design space exploration for aggressive test cost reduction in CircularScan architectures.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 9th European Test Symposium, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs.
IEEE Trans. Computers, 2003
J. Electron. Test., 2003
J. Electron. Test., 2003
IEEE Des. Test Comput., 2003
Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors.
IEEE Des. Test Comput., 2003
Guest Editors' Introduction: Application-Specific Microprocessors.
IEEE Des. Test Comput., 2003
Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 8th European Test Workshop, 2003
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
2002
ACM Trans. Design Autom. Electr. Syst., 2002
Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface.
J. Electron. Test., 2002
IEEE Des. Test Comput., 2002
IEEE Des. Test Comput., 2002
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Generic and Detailed Search for TAM Definition in Core-Based Systems.
Proceedings of the 3rd Latin American Test Workshop, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Proceedings of the 7th European Test Workshop, 2002
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
Proceedings of the 2002 Design, 2002
Power Efficient Embedded Processor Ip's through Application-Specific Tag Compression in Data Caches.
Proceedings of the 2002 Design, 2002
Proceedings of the 2002 Design, 2002
Energy frugal tags in reprogrammable I-caches for application-specific embedded processors.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
Performance and power effectiveness in embedded processors customizable partitioned caches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Improved Methods for Fault Diagnosis in Scan-Based BIST.
Proceedings of the 2nd Latin American Test Workshop, 2001
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
Testability implications in low-cost integrated radio transceivers: a Bluetooth case study.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
Data cache energy minimizations through programmable tag size matching to the applications.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors.
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001
Low-cost, software-based self-test methodologies for performance faults in processor control subsystems.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Block-Based Test Integration for Analog Integrated Circuits.
Proceedings of the 1st Latin American Test Workshop, 2000
Exploiting Off-Line Hierarchical Test Paths in Module Diagnosis and On-Line Test.
Proceedings of the 1st Latin American Test Workshop, 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Unifying methodologies for high fault coverage concurrent and off-line test of digital filters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Conference on Acoustics, 2000
Proceedings of the 5th European Test Workshop, 2000
Proceedings of the 5th European Test Workshop, 2000
Proceedings of the 2000 Design, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Modular test generation and concurrent transparency-based test translation using gate-level ATPG.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
Accumulation-based concurrent fault detection for linear digital state variable systems.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Proceedings of the 1999 Design, 1999
Proceedings of the 1999 Design, 1999
TRANSPARENT: a system for RTL testability analysis, DFT guidance and hierarchical test generation.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
1998
J. Electron. Test., 1998
J. Electron. Test., 1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
Proceedings of the 1998 Design, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
1997
Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction.
VLSI Design, 1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Proceedings of the Digest of Papers: FTCS-27, 1997
Proceedings of the 34st Conference on Design Automation, 1997
1996
Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors.
IEEE Trans. Reliab., 1996
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
Proceedings of the 33st Conference on Design Automation, 1996
1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Metric-based transformations for self testable VLSI designs with high test concurrency.
Proceedings of the Proceedings EURO-DAC'95, 1995
1994
Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures.
IEEE Trans. Very Large Scale Integr. Syst., 1994
Proceedings of the 7th International Symposium on High Level Synthesis, 1994
Integrating Binding Constraints in the Synthesis of Area-Efficient Self-Recovering Microarchitectures.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
Proceedings of the 31st Conference on Design Automation, 1994
Proceedings of the 31st Conference on Design Automation, 1994
1993
Intertwined Scheduling, Module Selection and Allocation in Time-and-Area.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Proceedings of the Digest of Papers: FTCS-23, 1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993
1992
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs.
Proceedings of the Digest of Papers: FTCS-22, 1992
Proceedings of the 29th Design Automation Conference, 1992
1991
Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991
1986
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986
1983
PhD thesis, 1983