Garo Bournoutian

According to our database1, Garo Bournoutian authored at least 10 papers between 2008 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2015
Mobile ecosystem driven application-specific low-power control microarchitecture.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Mobile Ecosystem Driven Dynamic Pipeline Adaptation for Low Power.
Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

2014
Architectural and Software Optimizations for Next- Generation Heterogeneous Low-Power Mobile Application Processors /.
PhD thesis, 2014

On-device objective-C application optimization framework for high-performance mobile processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Application-aware adaptive cache architecture for power-sensitive mobile processors.
ACM Trans. Embed. Comput. Syst., 2013

2012
Dynamic transient fault detection and recovery for embedded processor datapaths.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010
Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions.
Des. Autom. Embed. Syst., 2010

Dynamic, non-linear cache architecture for power-sensitive mobile processors.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2008
Miss reduction in embedded processors through dynamic, power-friendly cache design.
Proceedings of the 45th Design Automation Conference, 2008


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