Ge Zhang

According to our database, Ge Zhang authored at least 10 papers between 2005 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power.

Zichu Qi, Qi Guo, Ge Zhang, Xiangku Li, Weiwu Hu

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Optimizing power and throughput for m-out-of-n encoded asynchronous circuits.

Jun Xu, Ge Zhang, Weiwu Hu

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2008

A synchronized variable frequency clock scheme in chip multiprocessors.

Qifei Fan, Ge Zhang, Weiwu Hu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

An interconnect-aware power efficient cache coherence protocol for CMPs.

Hongbo Zeng, Jun Wang, Ge Zhang, Weiwu Hu

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor.

Jun Wang, Hongbo Zeng, Kun Huang, Ge Zhang, Yan Tang

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Reducing cache energy consumption by tag encoding in embedded processors.

Mingming Zhang, Xiaotao Chang, Ge Zhang

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

An Efficient Error Control Scheme for Chip-to-Chip Optical Interconnects.

Jun Wang, Ge Zhang, Weiwu Hu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Adaptive Clock Gating Technique for Low Power IP Core in SoC Design.

Xiaotao Chang, Mingming Zhang, Ge Zhang, Zhimin Zhang, Jun Wang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Parallel Error Detection for Leading Zero Anticipation.

Ge Zhang, Weiwu Hu, Zichu Qi

J. Comput. Sci. Technol., 2006

2005

A novel design of leading zero anticipation circuit with parallel error detection.

Ge Zhang, Zichu Qi, Weiwu Hu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005