George Higgins Hutchinson

Orcid: 0009-0002-2150-987X

According to our database1, George Higgins Hutchinson authored at least 11 papers between 2024 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Compressed High-Order Ising Machines.
IEEE J. Emerg. Sel. Topics Circuits Syst., June, 2026

PCIM-SAT: A 55nm Probabilistic K-SAT Solver with p-Bit-Based Parallel-Variable Update on a Mixed-Signal Compute-in-Memory Architecture.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025
Solving Boolean satisfiability problems with resistive content addressable memories.
CoRR, January, 2025

Controlling ReRAM's Switching Characteristics with Shadow Memory for Continual Learning.
Proceedings of the IEEE International Memory Workshop, 2025

KLIMA: Low-latency mixed-signal In-Memory Computing accelerator for solving arbitrary-order Boolean Satisfiability.
Proceedings of the IEEE Hot Chips 37 Symposium, 2025

Digital Annealing with Parallel Flip Dynamics.
Proceedings of the 59th Asilomar Conference on Signals, 2025

2024
Computing High-Degree Polynomial Gradients in Memory.
CoRR, 2024

FPIA: Field-Programmable Ising Arrays with In-Memory Computing.
CoRR, 2024

HO-FPIA: High-Order Field-Programmable Ising Arrays with In-Memory Computing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

FPIA: Field-Programmable Ising Arrays with In-Memory Computing.
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024

Memristor-based hardware and algorithms for higher-order Hopfield optimization solver outperforming quadratic Ising machines.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024


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