Dmitri B. Strukov
Orcid: 0000-0002-4526-4347Affiliations:
- University of California, Santa Barbara, USA
According to our database1,
Dmitri B. Strukov
authored at least 63 papers
between 2006 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
2023
Memristor-based hardware and algorithms for higher-order Hopfield optimization solver outperforming quadratic Ising machines.
CoRR, 2023
2021
The Impact of Device Uniformity on Functionality of Analog Passively-Integrated Memristive Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
3D-aCortex: an ultra-compact energy-efficient neurocomputing platform based on commercial 3D-NAND flash memories.
Neuromorph. Comput. Eng., 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Mixed-Signal Vector-by-Matrix Multiplier Circuits Based on 3D-NAND Memories for Neurocomputing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Energy-Efficient Time-Domain Vector-by-Matrix Multiplier for Neurocomputing and Beyond.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
CoRR, 2019
Preliminary Results Towards Reinforcement Learning with Mixed-Signal Memristive Neuromorphic Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Towards the Development of Analog Neuromorphic Chip Prototype with 2.4M Integrated Memristors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the International Joint Conference on Neural Networks, 2019
ChipSecure: A Reconfigurable Analog eFlash-Based PUF with Machine Learning Attack Resiliency in 55nm CMOS.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019
2018
High-Throughput Pattern Matching With CMOL FPGA Circuits: Case for Logic-in-Memory Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2018
High-Performance Mixed-Signal Neurocomputing With Nanoscale Floating-Gate Memory Cell Arrays.
IEEE Trans. Neural Networks Learn. Syst., 2018
Breaking POps/J Barrier with Analog Multiplier Circuits Based on Nonvolatile Memories.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
An ultra-low energy internally analog, externally digital vector-matrix multiplier based on NOR flash memory technology.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Implementation of Multilayer Perceptron Network with Highly Uniform Passive Memristive Crossbar Circuits.
CoRR, 2017
Capacity, Fidelity, and Noise Tolerance of Associative Spatial-Temporal Memories Based on Memristive Neuromorphic Network.
CoRR, 2017
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Memristor-based perceptron classifier: Increasing complexity and coping with imperfect hardware.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Utilizing I-V non-linearity and analog state variations in ReRAM-based security primitives.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
3D-DPE: A 3D high-bandwidth dot-product engine for high-performance neuromorphic computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
A 4-mm<sup>2</sup> 180-nm-CMOS 15-Giga-cell-updates-per-second DNA sequence alignment engine based on asynchronous race conditions.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
Highly-Secure Physically Unclonable Cryptographic Primitives Using Nonlinear Conductance and Analog State Tuning in Memristive Crossbar Arrays.
CoRR, 2016
Advancing Memristive Analog Neuromorphic Networks: Increasing Complexity, and Coping with Imperfect Hardware Components.
CoRR, 2016
Sub-1-us, Sub-20-nJ Pattern Classification in a Mixed-Signal Circuit Based on Embedded 180-nm Floating-Gate Memory Cell Arrays.
CoRR, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
Proceedings of the 46th European Solid-State Device Research Conference, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
IEEE Micro, 2015
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Efficient training algorithms for neural networks based on memristive crossbar circuits.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015
2014
Training and Operation of an Integrated Neuromorphic Network Based on Metal-Oxide Memristors.
CoRR, 2014
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014
2013
Digital-to-analog and analog-to-digital conversion with metal oxide memristors for ultra-low power computing.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Memristors for neural branch prediction: a case study in strict latency and write endurance challenges.
Proceedings of the Computing Frontiers Conference, 2013
2012
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applications.
Proceedings of the International Symposium on Physical Design, 2012
2011
High-Precision Tuning of State for Memristive Devices by Adaptable Variation-Tolerant Algorithm
CoRR, 2011
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2007
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007
2006
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006
CMOL FPGA circuits.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006