Gerard A. Allan

According to our database1, Gerard A. Allan authored at least 12 papers between 1992 and 2000.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2000
Yield prediction by sampling IC layout.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

IC Critical Volume Calculation through Ray-Casting of CSG Trees.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

1999
Efficient extra material critical area algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998
A Comparison of Efficient Dot Throwing and Shape Shifting Extra Material Critical Area Estimation.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1997
Efficient critical area estimation for arbitrary defect shapes.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996
Integration of DFM Techniques and Design Automation.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Application of a Survey Sampling Critical Area Computation Tool in a Manufacturing Environment.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Yield Prediction by Sampling with the EYES Tool.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995
Critical area extraction of extra material soft faults.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

Hierarchical critical area extraction with the EYE tool.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1994
Efficient Critical Area Algorithms and Their Application to Yield Improvement and Test Strategies.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1992
A yield improvement technique for IC layout using local design rules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992


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