Gerard M. Blair

According to our database1, Gerard M. Blair authored at least 6 papers between 1986 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2014
T2A: Clock implementation: A question of timing.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

2013
Equal length routing.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

1998
Reduced complexity two-phase micropipeline latch controller.
IEEE J. Solid State Circuits, 1998

1997
Comments on "New single-clock CMOS latches and flip-flops with improved speed and power savings".
IEEE J. Solid State Circuits, 1997

1996
Comments on "A robust single phase clocking for low power, high-speed VLSI applications" [and reply].
IEEE J. Solid State Circuits, 1996

1986
Content addressable memory : design and usage for general purpose computing.
PhD thesis, 1986


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