Ghulam M. Chaudhry

According to our database1, Ghulam M. Chaudhry authored at least 30 papers between 1989 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Renewable Energy Hybrid Grid-Connected System Sensitivity Analysis, Integration, and System Flexibility.
Proceedings of the 2019 IEEE International Symposium on Technology and Society, 2019

2007
Integrating firewire peripheral interface with an ethernet custom network processor.
Integr., 2007

Reliable Binary Signed Digit Number Adder Design.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Binary signed digit adder design with error detection capability.
Proceedings of the 9th International Symposium on Signal Processing and Its Applications, 2007

A Real-Time Hardware-Based Scheduler For Next-Generation Optical Burst Switches.
Proceedings of IEEE International Conference on Communications, 2007

DC Machine Control with Time Delay and a PID Controller.
Proceedings of the IEEE Conference on Automation Science and Engineering, 2007

Performance Evaluation of an Ultra-Fast Pipeline Scheduler for Next-Generation Networks.
Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007

QSDN: Quantum-dot cellular automata signed digit number adder.
Proceedings of the ISCA 20th International Conference on Parallel and Distributed Computing Systems, 2007

The performance of parallel prefix adders on nanometer FPGA.
Proceedings of the ISCA 20th International Conference on Parallel and Distributed Computing Systems, 2007

A multi-core architecture for bi-network protocol conversion.
Proceedings of the ISCA 20th International Conference on Parallel and Distributed Computing Systems, 2007

2006
Architecture and Performance of A Next-Generation Optical Burst Switch (OBS).
Proceedings of the 3rd International Conference on Broadband Communications, 2006

High-Speed Redundant Modulo 2n-1 Adder.
Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006

2004
SPEED: Stand-alone programmable ethernet enabled devices.
Microprocess. Microsystems, 2004

Routing framework for all-optical DWDM metro and long-haul transport networks with sparse wavelength conversion capabilities.
IEEE J. Sel. Areas Commun., 2004

Direct connect device core: design and applications.
Integr., 2004

Photonic Switching Techniques and Architecture for Next Generation Optical Networks.
Clust. Comput., 2004

Link-state update policies for all-optical DWDM transport networks.
Proceedings of IEEE International Conference on Communications, 2004

2003
Routing in all-optical DWDM networks with sparse wavelength conversion capabilities.
Proceedings of the Global Telecommunications Conference, 2003

2002
Performance analysis of IPSec protocol: encryption and authentication.
Proceedings of the IEEE International Conference on Communications, 2002

2001
TRON: the toolkit for routing in optical networks.
Proceedings of the Global Telecommunications Conference, 2001

Optimization of a Multi-Layer Perceptron Neural Network for Stock Market Forecasting.
Proceedings of the 14th International Conference on Computer Applications in Industry and Engineering, 2001

New Multiprotocol WDM/CDMA-Based Optical Switch Architecture.
Proceedings of the Proceedings 34th Annual Simulation Symposium (SS 2001), 2001

1999
Simulation of a Multicast ATM Switch for High-Speed Networks.
Simul., 1999

1998
CMA: A cell management algorithm for ATM networks.
Proceedings of the Computers and Their Applications (CATA-98), 1998

1996
Bandwidth of a reconfigurable multiple-group multiprocessor system.
J. Syst. Archit., 1996

1994
A case for the multithreaded processor architecture.
SIGARCH Comput. Archit. News, 1994

1992
On the bandwidth of asynchronous multiprocessors.
Microprocess. Microprogramming, 1992

1991
Performance of tightly-coupled systems with shared cache.
Microprocessing and Microprogramming, 1991

State Variable Model for a Class of Multiprocessor Systems.
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991

1989
On the efficiency of vector computers with private cache memories.
Microprocessing and Microprogramming, 1989


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