Gi-Moon Hong

According to our database1, Gi-Moon Hong authored at least 12 papers between 2010 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 3.2 Gb/s 16-Channel Transmitter for Intra-Panel Interfaces, With Independently Controllable Output Swing, Common-Mode Voltage, and Equalization.
IEEE Access, 2018

2017
A 0.13pJ/bit, referenceless transceiver with clock edge modulation for a wired intra-BAN communication.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2016
Phase shift keying demodulator with decision feedback phase-locked loop.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2013
Bitline Techniques With Dual Dynamic Nodes for Low-Power Register Files.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 10-Mbps 0.8-pJ/bit Referenceless Clock and Data Recovery Circuit for Optically Controlled Neural Interface System.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line.
Proceedings of the ESSCIRC 2013, 2013

2012
Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexers.
Integr., 2012

2011
A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A low-power referenceless clock and data recovery circuit with clock-edge modulation for biomedical sensor applications.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

2010
A fast-acquisition PLL using split half-duty sampled feedforward loop filter.
IEEE Trans. Consumer Electron., 2010


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