David Z. Pan

Zhixing Jiang

Hanqing Zhu

CoRR, 2023

Post-Layout Simulation Driven Analog Circuit Sizing.

[BibT_eX]

[DOI]

CoRR, 2023

Integrated multi-operand optical neurons for scalable and hardware-efficient deep learning.

[BibT_eX]

[DOI]

CoRR, 2023

DOTA: A Dynamically-Operated Photonic Tensor Core for Energy-Efficient Transformer Accelerator.

[BibT_eX]

[DOI]

CoRR, 2023

M3ICRO: Machine Learning-Enabled Compact Photonic Tensor Core based on PRogrammable Multi-Operand Multimode Interference.

[BibT_eX]

[DOI]

CoRR, 2023

QuantumSEA: In-Time Sparse Exploration for Noise Adaptive Quantum Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023

Pre-RMSNorm and Pre-CRMSNorm Transformers: Equivalent and Efficient Pre-LN Transformers.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

DREAMPlaceFPGA-PL: An Open-Source GPU-Accelerated Packer-Legalizer for Heterogeneous FPGAs.

[BibT_eX]

[DOI]

Mahesh A. Iyer

Proceedings of the 2023 International Symposium on Physical Design, 2023

Joint Optimization of Sizing and Layout for AMS Designs: Challenges and Opportunities.

[BibT_eX]

[DOI]

Proceedings of the 2023 International Symposium on Physical Design, 2023

Reinforcement Learning Guided Detailed Routing for Custom Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2023 International Symposium on Physical Design, 2023

Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks.

[BibT_eX]

[DOI]

Ahmet Faruk Budak

Keren Zhu

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

NormSoftmax: Normalizing the Input of Softmax to Accelerate and Stabilize Training.

[BibT_eX]

[DOI]

Jiaqi Gu

Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2023

Delving into Effective Gradient Matching for Dataset Condensation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2023

APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Light in AI: Toward Efficient Neurocomputing With Optical Neural Networks - A Tutorial.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Broadband Spectrum Channelizer With PWM-LO-Based Sub-Band Gain Control.

[BibT_eX]

[DOI]

Ki Yong Kim

Ranjit Gharpurey

IEEE J. Solid State Circuits, 2022

HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression.

[BibT_eX]

[DOI]

CoRR, 2022

QuEst: Graph Transformer for Quantum Circuit Reliability Estimation.

[BibT_eX]

[DOI]

CoRR, 2022

An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design.

[BibT_eX]

[DOI]

Saumyadip Mukhopadhyay

CoRR, 2022

Rethinking Graph Neural Networks for the Graph Coloring Problem.

[BibT_eX]

[DOI]

CoRR, 2022

On-chip QNN: Towards Efficient On-Chip Training of Quantum Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2022

NeurOLight: A Physics-Agnostic Neural Operator Enabling Parametric Photonic Device Simulation.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL.

[BibT_eX]

[DOI]

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

A Tale of EDA's Long Tail: Long-Tailed Distribution Learning for Electronic Design Automation.

[BibT_eX]

[DOI]

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

Challenges and Approaches in VLSI Routing.

[BibT_eX]

[DOI]

Gracieli Posser

Evangeline F. Y. Young

Stephan Held

Yih-Lang Li

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

EDAML 2022 Keynote Speaker: Machine Learning for Agile, Intelligent and Open-Source EDA.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

TorchQuantum Case Study for Robust Quantum Circuits.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

TAG: Learning Circuit Spatial Embedding from Layouts.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

QuantumNAS: Noise-Adaptive Search for Robust Quantum Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo Theories.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

A timing engine inspired graph neural network model for pre-routing slack prediction.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

ADEPT: automatic differentiable DEsign of photonic tensor cores.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

QOC: quantum on-chip training with parameter shift and gradient pruning.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

QuantumNAT: quantum noise-aware training with noise injection, quantization and normalization.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Multi-Scale High-Resolution Vision Transformer for Semantic Segmentation.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

ELight: Enabling Efficient Photonic In-Memory Neurocomputing with Life Enhancement.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit.

[BibT_eX]

[DOI]

Mahesh A. Iyer

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives: (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Automating Analog Constraint Extraction: From Heuristics to Learning: (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

OpenMPL: An Open-Source Layout Decomposer.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Toward Hardware-Efficient Optical Neural Networks: Beyond FFT Architecture via Joint Learnability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII.

[BibT_eX]

[DOI]

IEEE Des. Test, 2021

Silicon photonic subspace neural chip for hardware-efficient deep learning.

[BibT_eX]

[DOI]

CoRR, 2021

RoQNN: Noise-Aware Training for Robust Quantum Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2021

A New Acceleration Paradigm for Discrete CosineTransform and Other Fourier-Related Transforms.

[BibT_eX]

[DOI]

Jiaqi Gu

CoRR, 2021

Optimizer Fusion: Efficient Training with Better Locality and Parallelism.

[BibT_eX]

[DOI]

CoRR, 2021

L2ight: Enabling On-Chip Learning for Optical Neural Networks via Efficient in-situ Subspace Optimization.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021

Delving into Macro Placement with Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021

ADAPT: An Adaptive Machine Learning Framework with Application to Lithography Hotspot Detection.

[BibT_eX]

[DOI]

Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021

A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Towards Memory-Efficient Neural Networks via Multi-Level in situ Generation.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021

OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

O2NN: Optical Neural Networks with Differential Detection-Enabled Optical Operands.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

SqueezeLight: Towards Scalable Optical Neural Networks with Multi-Operand Ring Resonators.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Interactive Analog Layout Editing with Instant Placement Legalization.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks.

[BibT_eX]

[DOI]

Chandramouli V. Kashyap

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Efficient On-Chip Learning for Optical Neural Networks Through Power-Aware Sparse Zeroth-Order Optimization.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021

2020

Virtual-Tile-Based Flip-Flop Alignment Methodology for Clock Network Power Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Semisupervised Hotspot Detection With Self-Paced Multitask Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback.

[BibT_eX]

[DOI]

Shaolan Li

Nan Sun

IEEE J. Solid State Circuits, 2020

Report on the 38th ACM/IEEE International Conference on Computer-Aided Design (ICCAD 2019).

[BibT_eX]

[DOI]

IEEE Des. Test, 2020

TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix).

[BibT_eX]

[DOI]

CoRR, 2020

Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks.

[BibT_eX]

[DOI]

Jing Chen

IEEE Access, 2020

ML for CAD - Where is the Treasure Hiding?

[BibT_eX]

[DOI]

Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network.

[BibT_eX]

[DOI]

Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

TEMPO: Fast Mask Topography Effect Modeling with Deep Learning.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

DREAMPlace 3.0: Multi-Electrostatics Based Robust VLSI Placement with Region Constraints.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Re-examining VLSI Manufacturing and Yield through the Lens of Deep Learning : (Invited Talk).

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist.

[BibT_eX]

[DOI]

Yier Jin

Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

An Efficient Training Framework for Reversible Neural Architectures.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ECCV 2020, 2020

Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

ROQ: A Noise-Aware Quantization Scheme Towards Robust Optical Neural Networks with Low-bit Controls.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

SHIELDeNN: Online Accelerated Framework for Fault-Tolerant Deep Neural Network Architectures.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

FLOPS: EFficient On-Chip Learning for OPtical Neural Networks Through Stochastic Zeroth-Order Optimization.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Wafer Map Defect Patterns Classification using Deep Selective Learning.

[BibT_eX]

[DOI]

Duane S. Boning

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

High-Definition Routing Congestion Prediction for Large-Scale FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

IP Protection and Supply Chain Security through Logic Obfuscation: A Systematic Overview.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2019

Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups.

[BibT_eX]

[DOI]

Derong Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Provably Secure Camouflaging Strategy for IC Protection.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A New Paradigm for FPGA Placement Without Explicit Packing.

[BibT_eX]

[DOI]

Wuxi Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Device Layer-Aware Analytical Placement for Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2019 International Symposium on Physical Design, 2019

GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

Design Technology for Scalable and Robust Photonic Integrated Circuits: Invited Paper.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

IcySAT: Improved SAT-based Attacks on Cyclic Locked Circuits.

[BibT_eX]

[DOI]

Kaveh Shamsi

Yier Jin

Proceedings of the International Conference on Computer-Aided Design, 2019

elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs.

[BibT_eX]

[DOI]

Wuxi Li

Proceedings of the International Conference on Computer-Aided Design, 2019

Mixed Precision Neural Architecture Search for Energy Efficient Deep Learning.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

FPGA-Accelerated Spreading for Global Placement.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

On the Impossibility of Approximation-Resilient Circuit Locking.

[BibT_eX]

[DOI]

Kaveh Shamsi

Yier Jin

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

FPGA Accelerated FPGA Placement.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Simultaneous Placement and Clock Tree Construction for Modern FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Exploiting Wavelength Division Multiplexing for Optical Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection.

[BibT_eX]

[DOI]

Meng Li

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

KC2: Key-Condition Crunching for Fast Sequential Circuit Deobfuscation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Rethinking Sparsity in Performance Modeling for Analog and Mixed Circuits using Spike and Slab Models.

[BibT_eX]

[DOI]

Sinead A. Williamson

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

GAN-SRAF: Sub-Resolution Assist Feature Generation Using Conditional Generative Adversarial Networks.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

Hardware-software co-design of slimmed optical neural networks.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

LithoROC: lithography hotspot detection with explicit ROC optimization.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Tackling signal electromigration with learning-based detection and multistage mitigation.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

A shape-driven spreading algorithm using linear programming for global placement.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Semi-supervised hotspot detection with self-paced multi-task learning.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

S2-PM: semi-supervised learning for efficient performance modeling of analog and mixed signal circuits.

[BibT_eX]

[DOI]

Xiyuan Tang

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

OpenMPL: An Open Source Layout Decomposer: Invited Paper.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Graph-Based Redundant Via Insertion and Guiding Template Assignment for DSA-MP.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2018

Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Subresolution Assist Feature Generation With Supervised Data Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing.

[BibT_eX]

[DOI]

Wuxi Li

Shounak Dhar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint.

[BibT_eX]

[DOI]

Taehee Lee

Joon-Sung Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2018

Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD).

[BibT_eX]

[DOI]

Sri Parameswaran

R. Iris Bahar

IEEE Des. Test, 2018

OpenMPL: An Open Source Layout Decomposer.

[BibT_eX]

[DOI]

CoRR, 2018

Machine learning for IC design and technology co-optimization in extreme scaling.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on VLSI Design, 2018

Machine Learning for Yield Learning and Optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

TimingSAT: Decamouflaging Timing-based Logic Obfuscation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

Power Grid Reduction by Sparse Convex Optimization.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on Physical Design, 2018

Analog Placement Constraint Extraction and Exploration with the Application to Layout Retargeting.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on Physical Design, 2018

Data Efficient Lithography Modeling with Residual Neural Networks and Transfer Learning.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on Physical Design, 2018

GDP: GPU accelerated Detailed Placement.

[BibT_eX]

[DOI]

Shounak Dhar

Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

Cross-Lock: Dense Layout-Level Interconnect Locking using Cross-bar Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

OPERON: optical-electrical power-efficient route synthesis for on-chip signals.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

Logic synthesis for energy-efficient photonic integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Layout-dependent aging mitigation for critical path timing.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2017

Incremental Layer Assignment for Timing Optimization.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2017

Redundant Local-Loop Insertion for Unidirectional Routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Incremental Layer Assignment Driven by an External Signoff Timing Engine.

[BibT_eX]

[DOI]

José Luís Almada Güntzel

Luiz C. V. dos Santos

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Toward Unidirectional Routing Closure in Advanced Technology Nodes.

[BibT_eX]

[DOI]

Xiaoqing Xu

IPSJ Trans. Syst. LSI Des. Methodol., 2017

Stitch aware detailed placement for multiple E-beam lithography.

[BibT_eX]

[DOI]

Integr., 2017

PrivyNet: A Flexible Framework for Privacy-Preserving Deep Neural Network Training with A Fine-Grained Privacy Control.

[BibT_eX]

[DOI]

CoRR, 2017

Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

An Effective Timing-Driven Detailed Placement Algorithm for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Placement mitigation techniques for power grid electromigration.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Revisit sequential logic obfuscation: Attacks and defenses.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Patterning Aware Design Optimization of Selective Etching in N5 and Beyond.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

UTPlaceF 3.0: A parallelization framework for modern FPGA global placement: (Invited paper).

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

AppSAT: Approximately deobfuscating integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Circuit Obfuscation and Oracle-guided Attacks: Who can Prevail?

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Cyclic Obfuscation for Creating SAT-Unresolvable Circuits.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Concurrent Pin Access Optimization for Unidirectional Routing.

[BibT_eX]

[DOI]

Xiaoqing Xu

Proceedings of the 54th Annual Design Automation Conference, 2017

Streak: Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups.

[BibT_eX]

[DOI]

Derong Liu

Proceedings of the 54th Annual Design Automation Conference, 2017

Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault Attack.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Optical computing on silicon-on-insulator-based photonic integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

Layout Decomposition for Triple Patterning.

[BibT_eX]

[DOI]

Encyclopedia of Algorithms, 2016

Global Routing.

[BibT_eX]

[DOI]

Encyclopedia of Algorithms, 2016

EBL Overlapping Aware Stencil Planning for MCC System.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Design for manufacturability and reliability in extreme-scaling VLSI.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2016

A Machine Learning Based Framework for Sub-Resolution Assist Feature Generation.

[BibT_eX]

[DOI]

Proceedings of the 2016 on International Symposium on Physical Design, 2016

Concurrent Guiding Template Assignment and Redundant via Insertion for DSA-MP Hybrid Lithography.

[BibT_eX]

[DOI]

Jiaojiao Ou

Proceedings of the 2016 on International Symposium on Physical Design, 2016

A novel unified dummy fill insertion framework with SQP-based optimization method.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Detailed placement for modern FPGAs using 2D dynamic programming.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Incremental layer assignment for critical path timing.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Practical public PUF enabled by solving max-flow problem on chip.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Laplacian eigenmaps and bayesian clustering based layout pattern sampling and its applications to hotspot detection and OPC.

[BibT_eX]

[DOI]

Tetsuaki Matsunawa

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

Layout Decomposition for Triple Patterning Lithography.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure.

[BibT_eX]

[DOI]

Subhendu Roy

Pavlos M. Mattheakis

Laurent Masse-Navette

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

TILA: Timing-Driven Incremental Layer Assignment.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Toward Metrics of Design Automation Research Impact.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization.

[BibT_eX]

[DOI]

Laurent Masse-Navette

Pierre-Olivier Ribet

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Pushing multiple patterning in sub-10nm: are we ready?

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Machine learning and pattern matching in physical design.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Electromigration-aware redundant via insertion.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond.

[BibT_eX]

[DOI]

Naehyuck Chang

Yuan Xie

ACM Trans. Design Autom. Electr. Syst., 2014

Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Electromigration Study for Multiscale Power/Ground Vias in TSV-Based 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session).

[BibT_eX]

[DOI]

CoRR, 2014

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting.

[BibT_eX]

[DOI]

CoRR, 2014

Lithography Hotspot Detection and Mitigation in Nanometer VLSI.

[BibT_eX]

[DOI]

CoRR, 2014

Self-Aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement.

[BibT_eX]

[DOI]

CoRR, 2014

TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC.

[BibT_eX]

[DOI]

Commun. ACM, 2014

Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown.

[BibT_eX]

[DOI]

Subhendu Roy

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Timing-driven, over-the-block rectilinear steiner tree construction with pre-buffering and slew constraints.

[BibT_eX]

[DOI]

Yilin Zhang

Proceedings of the International Symposium on Physical Design, 2014

Layout Decomposition for Quadruple Patterning Lithography and Beyond.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

BOB-router: A new buffering-aware global router with over-the-block routing resources optimization.

[BibT_eX]

[DOI]

Yilin Zhang

Salim Chowdhury

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Self-aligned double patterning layout decomposition with complementary e-beam lithography.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Structure-Aware Placement Techniques for Designs With Datapaths.

[BibT_eX]

[DOI]

Myung-Chul Kim

Zhuo Li

Charles J. Alpert

Earl E. Swartzlander Jr.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Design for Manufacturing With Emerging Nanolithography.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations.

[BibT_eX]

[DOI]

Moongon Jung

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Chemical-Mechanical Polishing-Aware Application-Specific 3D NoC Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Skew Management of NBTI Impacted Gated Clock Trees.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Methodology for standard cell compliance and detailed placement for triple patterning lithography.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

A high-performance triple patterning layout decomposer with balanced density.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Clock power minimization using structured latch templates and decision tree induction.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

An accurate semi-analytical framework for full-chip TSV-induced stress modeling.

[BibT_eX]

[DOI]

Yang Li

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

L-shape based layout fracturing for e-beam lithography.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Lithography hotspot detection and mitigation in nanometer VLSI.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

UNISM: Unified Scheduling and Mapping for General Networks on Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

A3MAP: Architecture-aware analytic mapping for networks-on-chip.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

An accurate sparse-matrix based framework for statistical static timing analysis.

[BibT_eX]

[DOI]

Integr., 2012

VLSI CAD for emerging nanolithography.

[BibT_eX]

[DOI]

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Keep it straight: teaching placement how to better handle designs with datapaths.

[BibT_eX]

[DOI]

Myung-Chul Kim

Zhuo Li

Charles J. Alpert

Earl E. Swartzlander Jr.

Proceedings of the International Symposium on Physical Design, 2012

Flexible self-aligned double patterning aware detailed routing with prescribed layout planning.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2012

Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree construction.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper).

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Electromigration-aware routing for 3D ICs with stress-aware EM modeling.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

TRIAD: A triple patterning lithography aware detailed router.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

PADE: a high-performance placer with automatic datapath extraction and evaluation through high dimensional data learning.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs.

[BibT_eX]

[DOI]

Moongon Jung

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Design for manufacturability and reliability for TSV-based 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Robust Chip-Level Clock Tree Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Application-Aware NoC Design for Efficient SDRAM Access.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

High Performance Lithography Hotspot Detection With Successively Refined Pattern Identifications and Machine Learning.

[BibT_eX]

[DOI]

J. Andres Torres

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

A Voltage-Frequency Island Aware Energy Optimization Framework for Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Modeling of Layout Aware Line-Edge Roughness and Poly Optimization for Leakage Minimization.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

E-beam lithography stencil planning and optimization with overlapped characters.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Physical Design, 2011

Layout decomposition for triple patterning lithography.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Chemical-mechanical polishing aware application-specific 3D NoC design.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

Flexible 2D layout decomposition framework for spacer-type double pattering lithography.

[BibT_eX]

[DOI]

Kevin Lucas

Proceedings of the 48th Design Automation Conference, 2011

Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Exploration of VLSI CAD researches for early design rule evaluation.

[BibT_eX]

[DOI]

Chul-Hong Park

Kevin Lucas

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

High performance lithographic hotspot detection using hierarchically refined machine learning.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Controlling NBTI degradation during static burn-in testing.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization.

[BibT_eX]

[DOI]

Jae-Seok Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

An SDRAM-Aware Router for Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Manufacturability Aware Routing in Nanometer VLSI.

[BibT_eX]

[DOI]

Found. Trends Electron. Des. Autom., 2010

Total sensitivity based dfm optimization of standard library cells.

[BibT_eX]

[DOI]

Savithri Sundareswaran

Proceedings of the 2010 International Symposium on Physical Design, 2010

PASAP: power aware structured ASIC placement.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

WISDOM: Wire spreading enhanced decomposition of masks in Double Patterning Lithography.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Novel binary linear programming for high performance clock mesh synthesis.

[BibT_eX]

[DOI]

Ruchir Puri

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Stress-driven 3D-IC placement with TSV keep-out zone and regularity study.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

TSV stress aware timing analysis with applications to 3D-IC layout optimization.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture.

[BibT_eX]

[DOI]

Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

On stress aware active area sizing, gate sizing, and repeater insertion.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Physical Design, 2009

Analysis and optimization of NBTI induced clock skew in gated clock trees.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Double patterning lithography friendly detailed routing with redundant via consideration.

[BibT_eX]

[DOI]

Katrina Lu

Proceedings of the 46th Design Automation Conference, 2009

O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

RegPlace: a high quality open-source placement framework for structured ASICs.

[BibT_eX]

[DOI]

Anurag Kumar

Proceedings of the 46th Design Automation Conference, 2009

2008

Timing-Driven Placement.

[BibT_eX]

[DOI]

Bill Halpin

Haoxing Ren

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Manufacturability-Aware Routing.

[BibT_eX]

[DOI]

Joydeep Mitra

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Guest Editorial.

[BibT_eX]

[DOI]

Gi-Joon Nam

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Guest Editorial.

[BibT_eX]

[DOI]

Patrick H. Madden

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Track Routing and Optimization for Yield.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Metal-Density-Driven Placement for CMP Variation and Routability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Lithography friendly routing: from construct-by-correction to correct-by-construction.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Synergistic modeling and optimization for nanometer IC design/manufacturing integration.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

A high-performance droplet router for digital microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Physical Design, 2008

Overlay aware interconnect and timing variation modeling for double patterning technology.

[BibT_eX]

[DOI]

Jae-Seok Yang

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Nanolithography and CAD challenges for 32nm/22nm and beyond.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Pyramids: an efficient computational geometry-based approach for timing-driven placement.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A voltage-frequency island aware energy optimization framework for networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Double patterning technology friendly detailed routing.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Latch Modeling for Statistical Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Robust chip-level clock tree synthesis for SOC designs.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

An integrated nonlinear placement framework with congestion and porosity aware buffer planning.

[BibT_eX]

[DOI]

Tung-Chieh Chen

Proceedings of the 45th Design Automation Conference, 2008

Synthetic Biology Design and Analysis: A Case Study of Frequency Entrained Biological Clock.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Conference on Bioinformatics and Biomedicine, 2008

MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

DPlace2.0: A stable and efficient analytical placement based on diffusion.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Total power optimization combining placement, sizing and multi-Vt through slack distribution management.

[BibT_eX]

[DOI]

David Newmark

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Diffusion-Based Placement Migration With Application on Legalization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce.

[BibT_eX]

[DOI]

Anand Ramalingam

Anirudh Devgan

J. Low Power Electron., 2007

Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Accurate power grid analysis with behavioral transistor network modeling.

[BibT_eX]

[DOI]

Anand Ramalingam

Giri Devarayanadurg

Proceedings of the 2007 International Symposium on Physical Design, 2007

ISPD placement contest updates and ISPD 2007 global routing contest.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Physical Design, 2007

A novel intensity based optical proximity correction algorithm with speedup in lithography simulation.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

BoxRouter 2.0: architecture and implementation of a hybrid and robust global router.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

TROY: Track Router with Yield-driven Wire Planning.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

Hippocrates: First-Do-No-Harm Detailed Placement.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

DPlace: Anchor Cell-Based Quadratic Placement with Linear Objective.

[BibT_eX]

[DOI]

Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2006

PEAKASO: Peak-Temperature Aware Scan-Vector Optimization.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines.

[BibT_eX]

[DOI]

Andrew Havlir

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Variation tolerant buffered clock network synthesis with cross links.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Physical Design, 2006

Partial Functional Manipulation Based Wirelength Minimization.

[BibT_eX]

[DOI]

Avijit Dutta

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A unified non-rectangular device and circuit simulation model for timing and power.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Wire density driven global routing for CMP variation and timing.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Process variation aware OPC with variational lithography modeling.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

A new LP based incremental timing driven placement for high performance designs.

[BibT_eX]

[DOI]

David Newmark

Proceedings of the 43rd Design Automation Conference, 2006

Wire sizing with scattering effect for nanoscale interconnection.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Robust analytical gate delay modeling for low voltage circuits.

[BibT_eX]

[DOI]

Anand Ramalingam

Sreekumar V. Kodakara

Anirudh Devgan

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs.

[BibT_eX]

[DOI]

Hongjoong Shin

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Sensitivity guided net weighting for placement-driven synthesis.

[BibT_eX]

[DOI]

Haoxing Ren

David S. Kung

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Improved algorithms for link-based non-tree clock networks for skew variability reduction.

[BibT_eX]

[DOI]

Jiang Hu

Proceedings of the 2005 International Symposium on Physical Design, 2005

Computational geometry based placement migration.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

TACO: temperature aware clock-tree optimization.

[BibT_eX]

[DOI]

Suhail Ahmed

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Diffusion-based placement migration.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

RADAR: RET-aware detailed routing using fast lithography simulations.

[BibT_eX]

[DOI]

Joydeep Mitra

Proceedings of the 42nd Design Automation Conference, 2005

CMP aware shuttle mask floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Redundant-via enhanced maze routing for yield improvement.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Sleep transistor sizing using timing criticality and temporal currents.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

True crosstalk aware incremental placement with noise map.

[BibT_eX]

[DOI]

Haoxing Ren

Paul Villarrubia

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003

Multilevel global placement with congestion control.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Pushing ASIC performance in a power envelope.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

2002

Wire width planning for interconnect performance optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Physical hierarchy generation with routing congestion control.

[BibT_eX]

[DOI]

Chin-Chih Chang

Proceedings of 2002 International Symposium on Physical Design, 2002

2001

Interconnect performance estimation models for design planning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Interconnect sizing and spacing with consideration of couplingcapacitance.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Improved crosstalk modeling for noise constrained interconnect optimization.

[BibT_eX]

[DOI]

Prasanna V. Srinivas

Proceedings of ASP-DAC 2001, 2001

1999

Buffer block planning for interconnect-driven floorplanning.

[BibT_eX]

[DOI]

Tianming Kong

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Interconnect Estimation and Dlanning for Deep Submicron Designs.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Interconnect Delay Estimation Models for Synthesis and Design Planning.

[BibT_eX]

[DOI]