David Z. Pan

According to our database1, David Z. Pan authored at least 291 papers between 1997 and 2020.

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Bibliography

2020
Virtual-Tile-Based Flip-Flop Alignment Methodology for Clock Network Power Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Semisupervised Hotspot Detection With Self-Paced Multitask Learning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2020

A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure.
J. Solid-State Circuits, 2020

An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier.
J. Solid-State Circuits, 2020

An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback.
J. Solid-State Circuits, 2020

Report on the 38th ACM/IEEE International Conference on Computer-Aided Design (ICCAD 2019).
IEEE Des. Test, 2020

TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix).
CoRR, 2020

Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks.
IEEE Access, 2020

9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

TEMPO: Fast Mask Topography Effect Modeling with Deep Learning.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

ROQ: A Noise-Aware Quantization Scheme Towards Robust Optical Neural Networks with Low-bit Controls.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

High-Definition Routing Congestion Prediction for Large-Scale FPGAs.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
IP Protection and Supply Chain Security through Logic Obfuscation: A Systematic Overview.
ACM Trans. Design Autom. Electr. Syst., 2019

On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes.
IEEE Trans. Information Forensics and Security, 2019

Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Provably Secure Camouflaging Strategy for IC Protection.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

A New Paradigm for FPGA Placement Without Explicit Packing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Device Layer-Aware Analytical Placement for Analog Circuits.
Proceedings of the 2019 International Symposium on Physical Design, 2019

GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance.
Proceedings of the International Conference on Computer-Aided Design, 2019

Design Technology for Scalable and Robust Photonic Integrated Circuits: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019

MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019

IcySAT: Improved SAT-based Attacks on Cyclic Locked Circuits.
Proceedings of the International Conference on Computer-Aided Design, 2019

elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs.
Proceedings of the International Conference on Computer-Aided Design, 2019

Mixed Precision Neural Architecture Search for Energy Efficient Deep Learning.
Proceedings of the International Conference on Computer-Aided Design, 2019

FPGA-Accelerated Spreading for Global Placement.
Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

On the Impossibility of Approximation-Resilient Circuit Locking.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

FPGA Accelerated FPGA Placement.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Simultaneous Placement and Clock Tree Construction for Modern FPGAs.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Exploiting Wavelength Division Multiplexing for Optical Logic Synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

KC2: Key-Condition Crunching for Fast Sequential Circuit Deobfuscation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Rethinking Sparsity in Performance Modeling for Analog and Mixed Circuits using Spike and Slab Models.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

GAN-SRAF: Sub-Resolution Assist Feature Generation Using Conditional Generative Adversarial Networks.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

Hardware-software co-design of slimmed optical neural networks.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

LithoROC: lithography hotspot detection with explicit ROC optimization.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Tackling signal electromigration with learning-based detection and multistage mitigation.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

A shape-driven spreading algorithm using linear programming for global placement.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Semi-supervised hotspot detection with self-paced multi-task learning.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

S2-PM: semi-supervised learning for efficient performance modeling of analog and mixed signal circuits.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

OpenMPL: An Open Source Layout Decomposer: Invited Paper.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Graph-Based Redundant Via Insertion and Guiding Template Assignment for DSA-MP.
IEEE Trans. Very Large Scale Integr. Syst., 2018

UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine.
ACM Trans. Design Autom. Electr. Syst., 2018

Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Subresolution Assist Feature Generation With Supervised Data Learning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure.
J. Solid-State Circuits, 2018

Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD).
IEEE Des. Test, 2018

OpenMPL: An Open Source Layout Decomposer.
CoRR, 2018

Machine learning for IC design and technology co-optimization in extreme scaling.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

Machine Learning for Yield Learning and Optimization.
Proceedings of the IEEE International Test Conference, 2018

TimingSAT: Decamouflaging Timing-based Logic Obfuscation.
Proceedings of the IEEE International Test Conference, 2018

Power Grid Reduction by Sparse Convex Optimization.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Analog Placement Constraint Extraction and Exploration with the Application to Layout Retargeting.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Data Efficient Lithography Modeling with Residual Neural Networks and Transfer Learning.
Proceedings of the 2018 International Symposium on Physical Design, 2018

GDP: GPU accelerated Detailed Placement.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

Cross-Lock: Dense Layout-Level Interconnect Locking using Cross-bar Architectures.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

OPERON: optical-electrical power-efficient route synthesis for on-chip signals.
Proceedings of the 55th Annual Design Automation Conference, 2018

Logic synthesis for energy-efficient photonic integrated circuits.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Layout-dependent aging mitigation for critical path timing.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation.
ACM Trans. Design Autom. Electr. Syst., 2017

Incremental Layer Assignment for Timing Optimization.
ACM Trans. Design Autom. Electr. Syst., 2017

Redundant Local-Loop Insertion for Unidirectional Routing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Incremental Layer Assignment Driven by an External Signoff Timing Engine.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Toward Unidirectional Routing Closure in Advanced Technology Nodes.
IPSJ Trans. System LSI Design Methodology, 2017

Stitch aware detailed placement for multiple E-beam lithography.
Integr., 2017

PrivyNet: A Flexible Framework for Privacy-Preserving Deep Neural Network Training with A Fine-Grained Privacy Control.
CoRR, 2017

Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

An Effective Timing-Driven Detailed Placement Algorithm for FPGAs.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Placement mitigation techniques for power grid electromigration.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Revisit sequential logic obfuscation: Attacks and defenses.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Patterning Aware Design Optimization of Selective Etching in N5 and Beyond.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

UTPlaceF 3.0: A parallelization framework for modern FPGA global placement: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

AppSAT: Approximately deobfuscating integrated circuits.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Circuit Obfuscation and Oracle-guided Attacks: Who can Prevail?
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Cyclic Obfuscation for Creating SAT-Unresolvable Circuits.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology.
Proceedings of the 54th Annual Design Automation Conference, 2017

Concurrent Pin Access Optimization for Unidirectional Routing.
Proceedings of the 54th Annual Design Automation Conference, 2017

Streak: Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups.
Proceedings of the 54th Annual Design Automation Conference, 2017

Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault Attack.
Proceedings of the 54th Annual Design Automation Conference, 2017

Optical computing on silicon-on-insulator-based photonic integrated circuits.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Layout Decomposition for Triple Patterning.
Encyclopedia of Algorithms, 2016

Global Routing.
Encyclopedia of Algorithms, 2016

EBL Overlapping Aware Stencil Planning for MCC System.
ACM Trans. Design Autom. Electr. Syst., 2016

PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning.
ACM Trans. Design Autom. Electr. Syst., 2016

Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Design for manufacturability and reliability in extreme-scaling VLSI.
Sci. China Inf. Sci., 2016

A Machine Learning Based Framework for Sub-Resolution Assist Feature Generation.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

Concurrent Guiding Template Assignment and Redundant via Insertion for DSA-MP Hybrid Lithography.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

A novel unified dummy fill insertion framework with SQP-based optimization method.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Detailed placement for modern FPGAs using 2D dynamic programming.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Incremental layer assignment for critical path timing.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Practical public PUF enabled by solving max-flow problem on chip.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Laplacian eigenmaps and bayesian clustering based layout pattern sampling and its applications to hotspot detection and OPC.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography.
ACM Trans. Design Autom. Electr. Syst., 2015

Layout Decomposition for Triple Patterning Lithography.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

TILA: Timing-Driven Incremental Layer Assignment.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Toward Metrics of Design Automation Research Impact.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Pushing multiple patterning in sub-10nm: are we ready?
Proceedings of the 52nd Annual Design Automation Conference, 2015

High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Machine learning and pattern matching in physical design.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Electromigration-aware redundant via insertion.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond.
ACM Trans. Design Autom. Electr. Syst., 2014

Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Electromigration Study for Multiscale Power/Ground Vias in TSV-Based 3-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session).
CoRR, 2014

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting.
CoRR, 2014

Lithography Hotspot Detection and Mitigation in Nanometer VLSI.
CoRR, 2014

Self-Aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement.
CoRR, 2014

TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC.
Commun. ACM, 2014

Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Timing-driven, over-the-block rectilinear steiner tree construction with pre-buffering and slew constraints.
Proceedings of the International Symposium on Physical Design, 2014

Layout Decomposition for Quadruple Patterning Lithography and Beyond.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

BOB-router: A new buffering-aware global router with over-the-block routing resources optimization.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Self-aligned double patterning layout decomposition with complementary e-beam lithography.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Structure-Aware Placement Techniques for Designs With Datapaths.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Design for Manufacturing With Emerging Nanolithography.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Chemical-Mechanical Polishing-Aware Application-Specific 3D NoC Design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Skew Management of NBTI Impacted Gated Clock Trees.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Methodology for standard cell compliance and detailed placement for triple patterning lithography.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

A high-performance triple patterning layout decomposer with balanced density.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Clock power minimization using structured latch templates and decision tree induction.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

An accurate semi-analytical framework for full-chip TSV-induced stress modeling.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

L-shape based layout fracturing for e-beam lithography.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Lithography hotspot detection and mitigation in nanometer VLSI.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
UNISM: Unified Scheduling and Mapping for General Networks on Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A3MAP: Architecture-aware analytic mapping for networks-on-chip.
ACM Trans. Design Autom. Electr. Syst., 2012

E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

An accurate sparse-matrix based framework for statistical static timing analysis.
Integr., 2012

VLSI CAD for emerging nanolithography.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Keep it straight: teaching placement how to better handle designs with datapaths.
Proceedings of the International Symposium on Physical Design, 2012

Flexible self-aligned double patterning aware detailed routing with prescribed layout planning.
Proceedings of the International Symposium on Physical Design, 2012

Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree construction.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper).
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Electromigration-aware routing for 3D ICs with stress-aware EM modeling.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

TRIAD: A triple patterning lithography aware detailed router.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

PADE: a high-performance placer with automatic datapath extraction and evaluation through high dimensional data learning.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Design for manufacturability and reliability for TSV-based 3D ICs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Robust Chip-Level Clock Tree Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Application-Aware NoC Design for Efficient SDRAM Access.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

High Performance Lithography Hotspot Detection With Successively Refined Pattern Identifications and Machine Learning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

A Voltage-Frequency Island Aware Energy Optimization Framework for Networks-on-Chip.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Modeling of Layout Aware Line-Edge Roughness and Poly Optimization for Leakage Minimization.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

E-beam lithography stencil planning and optimization with overlapped characters.
Proceedings of the 2011 International Symposium on Physical Design, 2011

Layout decomposition for triple patterning lithography.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Chemical-mechanical polishing aware application-specific 3D NoC design.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection.
Proceedings of the 48th Design Automation Conference, 2011

Flexible 2D layout decomposition framework for spacer-type double pattering lithography.
Proceedings of the 48th Design Automation Conference, 2011

Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Exploration of VLSI CAD researches for early design rule evaluation.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

High performance lithographic hotspot detection using hierarchically refined machine learning.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Controlling NBTI degradation during static burn-in testing.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

An SDRAM-Aware Router for Networks-on-Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Manufacturability Aware Routing in Nanometer VLSI.
Found. Trends Electron. Des. Autom., 2010

Total sensitivity based dfm optimization of standard library cells.
Proceedings of the 2010 International Symposium on Physical Design, 2010

PASAP: power aware structured ASIC placement.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

WISDOM: Wire spreading enhanced decomposition of masks in Double Patterning Lithography.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Novel binary linear programming for high performance clock mesh synthesis.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Stress-driven 3D-IC placement with TSV keep-out zone and regularity study.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

TSV stress aware timing analysis with applications to 3D-IC layout optimization.
Proceedings of the 47th Design Automation Conference, 2010

Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography.
Proceedings of the 47th Design Automation Conference, 2010

A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability.
ACM Trans. Design Autom. Electr. Syst., 2009

ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture.
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

On stress aware active area sizing, gate sizing, and repeater insertion.
Proceedings of the 2009 International Symposium on Physical Design, 2009

Analysis and optimization of NBTI induced clock skew in gated clock trees.
Proceedings of the Design, Automation and Test in Europe, 2009

Double patterning lithography friendly detailed routing with redundant via consideration.
Proceedings of the 46th Design Automation Conference, 2009

O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration.
Proceedings of the 46th Design Automation Conference, 2009

RegPlace: a high quality open-source placement framework for structured ASICs.
Proceedings of the 46th Design Automation Conference, 2009

2008
Timing-Driven Placement.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Manufacturability-Aware Routing.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Guest Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Guest Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Track Routing and Optimization for Yield.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Metal-Density-Driven Placement for CMP Variation and Routability.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Lithography friendly routing: from construct-by-correction to correct-by-construction.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Synergistic modeling and optimization for nanometer IC design/manufacturing integration.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

A high-performance droplet router for digital microfluidic biochips.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Overlay aware interconnect and timing variation modeling for double patterning technology.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Nanolithography and CAD challenges for 32nm/22nm and beyond.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Pyramids: an efficient computational geometry-based approach for timing-driven placement.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A voltage-frequency island aware energy optimization framework for networks-on-chip.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Double patterning technology friendly detailed routing.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Latch Modeling for Statistical Timing Analysis.
Proceedings of the Design, Automation and Test in Europe, 2008

Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices.
Proceedings of the Design, Automation and Test in Europe, 2008

Robust chip-level clock tree synthesis for SOC designs.
Proceedings of the 45th Design Automation Conference, 2008

ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction.
Proceedings of the 45th Design Automation Conference, 2008

An integrated nonlinear placement framework with congestion and porosity aware buffer planning.
Proceedings of the 45th Design Automation Conference, 2008

Synthetic Biology Design and Analysis: A Case Study of Frequency Entrained Biological Clock.
Proceedings of the 2008 IEEE International Conference on Bioinformatics and Biomedicine, 2008

MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

DPlace2.0: A stable and efficient analytical placement based on diffusion.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Total power optimization combining placement, sizing and multi-Vt through slack distribution management.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Diffusion-Based Placement Migration With Application on Legalization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce.
J. Low Power Electron., 2007

Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Accurate power grid analysis with behavioral transistor network modeling.
Proceedings of the 2007 International Symposium on Physical Design, 2007

ISPD placement contest updates and ISPD 2007 global routing contest.
Proceedings of the 2007 International Symposium on Physical Design, 2007

A novel intensity based optical proximity correction algorithm with speedup in lithography simulation.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

BoxRouter 2.0: architecture and implementation of a hybrid and robust global router.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis.
Proceedings of the 44th Design Automation Conference, 2007

TROY: Track Router with Yield-driven Wire Planning.
Proceedings of the 44th Design Automation Conference, 2007

Hippocrates: First-Do-No-Harm Detailed Placement.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

DPlace: Anchor Cell-Based Quadratic Placement with Linear Objective.
Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2006
PEAKASO: Peak-Temperature Aware Scan-Vector Optimization.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Variation tolerant buffered clock network synthesis with cross links.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Partial Functional Manipulation Based Wirelength Minimization.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A unified non-rectangular device and circuit simulation model for timing and power.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Wire density driven global routing for CMP variation and timing.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Process variation aware OPC with variational lithography modeling.
Proceedings of the 43rd Design Automation Conference, 2006

A new LP based incremental timing driven placement for high performance designs.
Proceedings of the 43rd Design Automation Conference, 2006

Wire sizing with scattering effect for nanoscale interconnection.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Robust analytical gate delay modeling for low voltage circuits.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Sensitivity guided net weighting for placement-driven synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Improved algorithms for link-based non-tree clock networks for skew variability reduction.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Computational geometry based placement migration.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

TACO: temperature aware clock-tree optimization.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Diffusion-based placement migration.
Proceedings of the 42nd Design Automation Conference, 2005

RADAR: RET-aware detailed routing using fast lithography simulations.
Proceedings of the 42nd Design Automation Conference, 2005

CMP aware shuttle mask floorplanning.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Redundant-via enhanced maze routing for yield improvement.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Sleep transistor sizing using timing criticality and temporal currents.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
True crosstalk aware incremental placement with noise map.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003
Multilevel global placement with congestion control.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Pushing ASIC performance in a power envelope.
Proceedings of the 40th Design Automation Conference, 2003

2002
Wire width planning for interconnect performance optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Physical hierarchy generation with routing congestion control.
Proceedings of 2002 International Symposium on Physical Design, 2002

2001
Interconnect performance estimation models for design planning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Interconnect sizing and spacing with consideration of couplingcapacitance.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Improved crosstalk modeling for noise constrained interconnect optimization.
Proceedings of ASP-DAC 2001, 2001

1999
Buffer block planning for interconnect-driven floorplanning.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Interconnect Estimation and Dlanning for Deep Submicron Designs.
Proceedings of the 36th Conference on Design Automation, 1999

Interconnect Delay Estimation Models for Synthesis and Design Planning.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1997
Interconnect design for deep submicron ICs.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Global interconnect sizing and spacing with consideration of coupling capacitance.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997


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