Giho Park

Orcid: 0000-0001-7998-4302

According to our database1, Giho Park authored at least 18 papers between 2011 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
Lightweight Look-ahead Multi-context Vision Transformer.
Proceedings of the International Conference on Electronics, Information, and Communication, 2025

2023
CaMeL-Net: Centroid-aware metric learning for efficient multi-class cancer classification in pathology images.
Comput. Methods Programs Biomed., November, 2023

An Integrated Solution to Improve Performance of In-Memory Data Caching With an Efficient Item Retrieving Mechanism and a Near-Memory Accelerator.
IEEE Access, 2023

2022
A Low-power Programmable Machine Learning Hardware Accelerator Design for Intelligent Edge Devices.
ACM Trans. Design Autom. Electr. Syst., 2022

2018
An adaptive cache replacement policy based on fine-grain reusability monitor.
IEICE Electron. Express, 2018

2017
Triple Engine Processor (TEP): A Heterogeneous Near-Memory Processor for Diverse Kernel Operations.
ACM Trans. Archit. Code Optim., 2017

An analytical model based on performance demand of workload for energy-efficient heterogeneous multicore systems.
J. Parallel Distributed Comput., 2017

Sensor data compression and power management scheme for low power sensor hub.
IEICE Electron. Express, 2017

Intelligence Boosting Engine (IBE): A hardware accelerator for processing sensor fusion and machine learning algorithm for a sensor hub SoC.
Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017

JUMPRUN: A hybrid mechanism to accelerate item scanning for in-memory databases.
Proceedings of the 2017 IEEE International Conference on Big Data and Smart Computing, 2017

2016
Cooperative cache memory (CCM) based on the performance efficiency for 3D stacked memory system.
IEICE Electron. Express, 2016

2015
Accelerating Application Start-up with Nonvolatile Memory in Android Systems.
IEEE Micro, 2015

2014
A simulation-based framework for the generation and evaluation of traffic management strategies.
Proceedings of the 47th Annual Simulation Symposium, 2014

2013
An adaptive L2 cache prefetching mechanism for effective exploitation of abundant memory bandwidth of 3-D IC technology.
IEICE Electron. Express, 2013

Versatile stream buffer architecture to exploit the high memory bandwidth of 3-D IC technology.
IEICE Electron. Express, 2013

Symbiotic Simulation for the Generation and Simulation of Incident Management Strategies.
Proceedings of the AsiaSim 2013, 2013

Phase detection based data prefetching for utilizing memory bandwidth of 3D integrated circuits.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2011
Adaptive prefetching scheme for exploiting massive memory bandwidth of 3-D IC technology.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011


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