Gopinath Narayanan Pandurangan

According to our database, Gopinath Narayanan Pandurangan authored at least 3 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Dynamic Voltage Boosting Seven-Level Dual Ground Inverter Topology With Low Voltage Stress on Components.

Gopinath Narayanan Pandurangan, Jagabar Sathik Mohamed Ali, Vigna K. Ramachandaramurthy, Mamdouh L. Alghaythi, Saad Mekhilef

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2026

2024

Improved Dual Boost Mid-Point Clamped Five-Level Inverter Topology.

M. Jagabar Sathik, Gopinath Narayanan Pandurangan, Arpan Hota, K. Vijayakumar, Saad Mekhilef, Vivek Agarwal

IEEE Trans. Circuits Syst. II Express Briefs, June, 2024

2023

A 7L and 11L High Step-Up SCMLI Topology With Reduced Component Voltage Stress.

Jagabar Sathik Mohamed Ali, Amjad Rehman Khan, Gopinath Narayanan Pandurangan, Prem Ponnusamy, Faten S. Alamri, Saeed Ali Bahaj

IEEE Access, 2023