Mohamed Ali Jagabar Sathik
Orcid: 0000-0002-4247-8972Affiliations:
- SRM Institute of Science and Technology, Chennai, India
According to our database1,
Mohamed Ali Jagabar Sathik
authored at least 33 papers
between 2018 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
2023
Int. J. Circuit Theory Appl., November, 2023
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
A New Boost Topology Seven-Level Inverter of High Voltage Gain Ability and Continuous Input Current With MPPT for PV Grid Integration.
IEEE Access, 2023
IEEE Access, 2023
2022
Improved Performance of Hybrid PV and Wind Generating System Connected to the Grid Using Finite-Set Model Predictive Control.
IEEE Access, 2022
IEEE Access, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A New Switched-Ladder Multilevel Converter Structure with Reduced Power Electronic Components.
J. Circuits Syst. Comput., 2021
Design of nine step switched capacitor multilevel inverter and its cascaded extension.
Int. J. Circuit Theory Appl., 2021
A new generalized cascade multilevel converter topology and its improved modulation technique.
Int. J. Circuit Theory Appl., 2021
Experimental validation of nine-level switched-capacitor inverter topology with high voltage gain.
Int. J. Circuit Theory Appl., 2021
Performance improvement of solar PV power conversion system through low duty cycle DC-DC converter.
Int. J. Circuit Theory Appl., 2021
Modified LUO High Gain DC-DC Converter With Minimal Capacitor Stress for Electric Vehicle Application.
IEEE Access, 2021
A New Hybrid Zeta-Boost Converter With Active Quad Switched Inductor for High Voltage Gain.
IEEE Access, 2021
IEEE Access, 2021
2020
A New Switched Capacitor 7L Inverter With Triple Voltage Gain and Low Voltage Stress.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst., 2020
Cross Connected Compact Switched-Capacitor Multilevel Inverter (C<sup>3</sup>-SCMLI) Topology With Reduced Switch Count.
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Improved "K" type seven-level switched capacitor inverter topology with Self-voltage balancing.
Int. J. Circuit Theory Appl., 2020
A new generalized switched diode multilevel inverter topology with reduced switch count and voltage on switches.
Int. J. Circuit Theory Appl., 2020
A Single DC Source Nine-Level Switched-Capacitor Boost Inverter Topology With Reduced Switch Count.
IEEE Access, 2020
A New Multilevel Inverter Topology With Reduced Power Components for Domestic Solar PV Applications.
IEEE Access, 2020
A New Eight Switch Seven Level Boost Active Neutral Point Clamped (8S-7L-BANPC) Inverter.
IEEE Access, 2020
An Original Hybrid Multilevel DC-AC Converter Using Single-Double Source Unit for Medium Voltage Applications: Hardware Implementation and Investigation.
IEEE Access, 2020
IEEE Access, 2020
2019
A New Asymmetric and Cascaded Switched Diode Multilevel Inverter Topology for Reduced Switches, DC Source and Blocked Voltage on Switches.
J. Circuits Syst. Comput., 2019
A New Single Phase Single Switched-Capacitor Based Nine-Level Boost Inverter Topology With Reduced Switch Count and Voltage Stress.
IEEE Access, 2019
A New 5-Level ANPC Switched Capacitor Inverter Topology for Photovoltaic Applications.
Proceedings of the IECON 2019, 2019
2018
Three-Dimensional Space Vector Modulation Strategy for Capacitor Balancing in Split Inductor Neutral-Point Clamped Multilevel Inverters.
J. Circuits Syst. Comput., 2018