Goran Lj. Djordjevic

According to our database1, Goran Lj. Djordjevic authored at least 20 papers between 1996 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
Multi-algorithm UWB-based localization method for mixed LOS/NLOS environments.
Comput. Commun., 2022

2021
Optimal port allocation scheme for deflection-routed networks-on-chip.
J. Supercomput., 2021

Fingerprinting-assisted UWB-based localization technique for complex indoor environments.
Expert Syst. Appl., 2021

2020
Tone-Based Contention Resolution for Multi-hop Wireless Sensor Networks.
Wirel. Pers. Commun., 2020

Token ring arbitration scheme for on-chip CDMA bus architectures.
Microelectron. J., 2020

2016
Improving fault-tolerance capability of on-chip binary CDMA bus.
J. Supercomput., 2016

Intra-cluster tone-based contention resolution mechanism for wireless sensor networks.
Comput. Electr. Eng., 2016

2015
Dual-mode inter-router communication channel for deflection-routed networks-on-chip.
J. Supercomput., 2015

2014
Reduced-frame TDMA protocols for wireless sensor networks.
Int. J. Commun. Syst., 2014

Range-Free Localization in Wireless Sensor Networks Using Fuzzy Logic.
Ad Hoc Sens. Wirel. Networks, 2014

2012
Fuzzy ring-overlapping range-free (FRORF) localization method for wireless sensor networks.
Comput. Commun., 2012

2009
CDMA bus-based on-chip interconnect infrastructure.
Microelectron. Reliab., 2009

2005
A mid-value select voter.
Microelectron. Reliab., 2005

2004
Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits.
Microelectron. Reliab., 2004

Approach to partially self-checking combinational circuits design.
Microelectron. J., 2004

2001
Loose composite constraint codes and their application in DVD.
IEEE J. Sel. Areas Commun., 2001

1998
The asynchronous counterflow pipeline bit-serial multiplier.
J. Syst. Archit., 1998

1996
A Heuristic for Scheduling Task Graphs with Communication Delays Onto Multiprocessors.
Parallel Comput., 1996

A Compile-Time Scheduling Heuristic for Multiprocessor Architectures.
Comput. J., 1996

An Interprocessor Communication Interface for Message Passing via Shared Memory Modules - Design and Performance.
Comput. Artif. Intell., 1996


  Loading...