Goro Suzuki

According to our database, Goro Suzuki authored at least 7 papers between 1990 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Waveform base clock tree delay analysis using parallel processing.

Goro Suzuki

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013

Multiple terminal reduction method.

Goro Suzuki

Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Interconnect waveform calculation method with parameter variation.

Goro Suzuki, Ryo Yamanaka

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2011

Separate projection and extended Cauer method for circuit reduction.

Goro Suzuki

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

VLSI interconnect delay analysis method for ramp input signal.

Nobuyuki Mihara, Goro Suzuki

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

1992

MOSAIC: a tile-based datapath layout generator.

Goro Suzuki, Tetsuya Yamamoto, Kyoji Yuyama, Kotaro Hirasawa

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1990

A Practical Online Design Rule Checking System.

Goro Suzuki, Yoshio Okamura

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990