Grzegorz Pastuszak

According to our database, Grzegorz Pastuszak authored at least 40 papers between 2004 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Quantifier elimination theory and maps which preserve semipositivity.

Grzegorz Pastuszak, Adam Skowyrski, Andrzej Jamiolkowski

Quantum Inf. Process., 2021

2020

Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders.

Grzegorz Pastuszak

IEEE Trans. Very Large Scale Integr. Syst., 2020

Generative Multi-Symbol Architecture of the Binary Arithmetic Coder for UHDTV Video Encoders.

Grzegorz Pastuszak

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2016

Optimization of the Adaptive Computationally-Scalable Motion Estimation and Compensation for the Hardware H.264/AVC Encoder.

Grzegorz Pastuszak, Mariusz H. Jakubowski

J. Signal Process. Syst., 2016

Algorithm and Architecture Design of the H.265/HEVC Intra Encoder.

Grzegorz Pastuszak, Andrzej Abramowski

IEEE Trans. Circuits Syst. Video Technol., 2016

On a Criterion for Simultaneous Block-Diagonalization of Normal Matrices.

Grzegorz Pastuszak, Takeo Kamizawa, Andrzej Jamiolkowski

Open Syst. Inf. Dyn., 2016

Algorithm and architecture design of the motion estimation for the H.265/HEVC 4K-UHD encoder.

Grzegorz Pastuszak, Maciej Trochimiuk

J. Real Time Image Process., 2016

Architecture design of the high-throughput compensator and interpolator for the H.265/HEVC encoder.

Grzegorz Pastuszak, Maciej Trochimiuk

J. Real Time Image Process., 2016

2015

Architecture Design of the H.264/AVC Encoder Based on Rate-Distortion Optimization.

Grzegorz Pastuszak

IEEE Trans. Circuits Syst. Video Technol., 2015

Hardware architectures for the H.265/HEVC discrete cosine transform.

Grzegorz Pastuszak

IET Image Process., 2015

Flexible Architecture Design for H.265/HEVC Inverse Transform.

Grzegorz Pastuszak

Circuits Syst. Signal Process., 2015

2014

Intra Prediction for the Hardware H.264/AVC High Profile Encoder.

Mikolaj Roszkowski, Grzegorz Pastuszak

J. Signal Process. Syst., 2014

FPGA design of the computation unit for the semi-global stereo matching algorithm.

Mikolaj Roszkowski, Grzegorz Pastuszak

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

FPGA architectures of the quantization and the dequantization for video encoders.

Grzegorz Pastuszak

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

A double-path intra prediction architecture for the hardware H.265/HEVC encoder.

Andrzej Abramowski, Grzegorz Pastuszak

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013

Adaptive Computationally Scalable Motion Estimation for the Hardware H.264/AVC Encoder.

Grzegorz Pastuszak, Mariusz H. Jakubowski

IEEE Trans. Circuits Syst. Video Technol., 2013

Architecture Design and Efficiency Evaluation for the High-Throughput Interpolation in the HEVC Encoder.

Grzegorz Pastuszak, Maciej Trochimiuk

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A Novel Intra Prediction Architecture for the Hardware HEVC Encoder.

Andrzej Abramowski, Grzegorz Pastuszak

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

Hardware implementation of adaptive motion estimation and compensation for H.264/AVC.

Grzegorz Pastuszak, Mariusz H. Jakubowski

Proceedings of the 2012 Picture Coding Symposium, 2012

2010

Data Reuse in Two-level Hierarchical Motion Estimation for High Resolution Video Coding.

Mariusz H. Jakubowski, Grzegorz Pastuszak

Proceedings of the SIGMAP 2010, 2010

Intra prediction hardware module for high-profile H.264/AVC decoder.

Mikolaj Roszkowski, Grzegorz Pastuszak

Proceedings of the 10th IFAC Workshop on Programmable Devices and Embedded Systems, 2010

Stream header decoder and context-adaptive variable-length decoder hardware module for H.264/AVC codec.

Grzegorz Pastuszak, Michal Wieczorek

Proceedings of the 10th IFAC Workshop on Programmable Devices and Embedded Systems, 2010

Hardware implementation of the transformation module of the MPEG-4 AAC standard.

Grzegorz Brzuchalski, Grzegorz Pastuszak

Proceedings of the 10th IFAC Workshop on Programmable Devices and Embedded Systems, 2010

Context-adaptive binary arithmetic decoder architecture for H.264/AVC.

Andrzej Abramowski, Grzegorz Pastuszak

Proceedings of the 10th IFAC Workshop on Programmable Devices and Embedded Systems, 2010

2009

An Adaptive Computation-aware Algorithm for Multi-frame Variable Block-size Motion Estimation in H.264/AVC.

Mariusz H. Jakubowski, Grzegorz Pastuszak

Proceedings of the SIGMAP 2009, 2009

2008

A High-Performance Architecture of the Double-Mode Binary Coder for H.264.AVC.

Grzegorz Pastuszak

IEEE Trans. Circuits Syst. Video Technol., 2008

Constant Bitrate Control for a Distributed Video Coding System.

Mariusz H. Jakubowski, João Ascenso, Grzegorz Pastuszak

Proceedings of the SIGMAP 2008, 2008

Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode Selection.

Grzegorz Pastuszak

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007

Architecture Design of the Double-Mode Binarization for High-Profile H.264/AVC Compression.

Grzegorz Pastuszak

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Rate Control for Multi-Sequence H.264/AVC Compression.

Andrzej Pietrasiewicz, Grzegorz Pastuszak

Proceedings of the SIGMAP 2007, 2007

Multi-sequence H.264/AVC Rate Control Based on the Linear Model.

Grzegorz Pastuszak, Andrzej Pietrasiewicz

Proceedings of the E-business and Telecommunications - 4th International Conference, 2007

2006

Parallel Symbol Architectures for H.264/AVC Binary Coder Based on Arithmetic Coding.

Grzegorz Pastuszak

Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

Architecture Design for the Context Formatter in the H.264/AVC Encoder.

Grzegorz Pastuszak

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

A hardware-oriented analysis of arithmetic coding - comparative study of JPEG2000 and H.264/AVC comppression standards.

Grzegorz Pastuszak

Proceedings of the e-Business and Telecommunication Networks, 2006

2005

A high-performance architecture for embedded block coding in JPEG 2000.

Grzegorz Pastuszak

IEEE Trans. Circuits Syst. Video Technol., 2005

A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000.

Grzegorz Pastuszak

Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, 2005

Efficient Hardware Architecture for EBCOT in JPEG 2000 Using a Feedback Loop from the Rate Controller to the Bit-Plane Coder.

Grzegorz Pastuszak

Proceedings of the Image Analysis and Processing, 2005

2004

A Novel Architecture of Arithmetic Coder in JPEG2000 Based on Parallel Symbol Encoding.

Grzegorz Pastuszak

Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

A high-performance architecture of arithmetic coder in JPEG2000.

Grzegorz Pastuszak

Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004

Hardware-Oriented Analysis of the Arithmetic Coding - Comparative Study of JPEG2000 and H.264/AVC Compression Standards.

Grzegorz Pastuszak

Proceedings of the ICETE 2004, 2004