Hajer Najjar

According to our database1, Hajer Najjar authored at least 3 papers between 2015 and 2018.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
A Reusable Hybrid RISC Processor with Programmable Instruction Set.
Proceedings of the 15th International Multi-Conference on Systems, Signals & Devices, 2018

2016
A new programmable ALU architecture for hard-core processor.
Proceedings of the 13th International Multi-Conference on Systems, Signals & Devices, 2016

2015
Implementation of a baseline RISC for the realization of a dynamically reconfigurable processor.
Proceedings of the 12th IEEE International Multi-Conference on Systems, Signals & Devices, 2015


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