Han Cho

Orcid: 0009-0000-9010-7888

According to our database1, Han Cho authored at least 6 papers between 2007 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2025
Sub 4-bit Power-of-Two-Based Mixed-Precision Quantization for Efficient LLM Compression and Acceleration.
IEEE Access, 2025

DPP-ViT: Dynamic Patch Pruning for Low Complexity Vision Transformer Accelerator.
Proceedings of the 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2025

2024
iSPADE: End-to-end Sparse Architecture for Dense DNN Acceleration via Inverted-bit Representation.
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024

SpARC: Token Similarity-Aware Sparse Attention Transformer Accelerator via Row-wise Clustering.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2022
Channel-Wise Activation Map Pruning using Max-Pool for Reducing Memory Accesses.
Proceedings of the 19th International SoC Design Conference, 2022

2007
Dressing and modeling food.
Proceedings of the International Conference on Computer Graphics and Interactive Techniques, 2007


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