Saibal Mukhopadhyay
Orcid: 0000-0002-8894-3390Affiliations:
- Georgia Institute of Technology, Atlanta GA, USA
According to our database1,
Saibal Mukhopadhyay
authored at least 309 papers
between 2002 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2018, "For contributions to energy-efficient and robust computing systems design".
Timeline
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Online presence:
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on orcid.org
On csauthors.net:
Bibliography
2024
Topological Representations of Heterogeneous Learning Dynamics of Recurrent Spiking Neural Networks.
CoRR, 2024
Sparse Spiking Neural Network: Exploiting Heterogeneity in Timescales for Pruning Recurrent SNN.
CoRR, 2024
Studying the Impact of Stochasticity on the Evaluation of Deep Neural Networks for Forest-Fire Prediction.
CoRR, 2024
STEMFold: Stochastic Temporal Manifold for Multi-Agent Interactions in the Presence of Hidden Agents.
CoRR, 2024
Modulation Recognition with Untrained Deep Neural Network for IoT and Mobile Applications.
Proceedings of the IEEE Radio and Wireless Symposium, 2024
BeamCIM: A Compute-In-Memory based Broadband Beamforming Accelerator using Linear Embedding.
Proceedings of the IEEE Radio and Wireless Symposium, 2024
2023
XMD: An Expansive Hardware-Telemetry-Based Mobile Malware Detector for Endpoint Detection.
IEEE Trans. Inf. Forensics Secur., 2023
IEEE Robotics Autom. Lett., 2023
On-Chip Acceleration of RF Signal Modulation Classification With Short-Time Fourier Transform and Convolutional Neural Network.
IEEE Access, 2023
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
A 32.5mW Mixed-Signal Processing-in-Memory-Based k-SAT Solver in 65nm CMOS with 74.0% Solvability for 3D-Variable 126-Clause 3-SAT Problems.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
CLUE: Cross-Layer Uncertainty Estimator for Reliable Neural Perception using Processing-in-Memory Accelerators.
Proceedings of the International Joint Conference on Neural Networks, 2023
Proceedings of the International Joint Conference on Neural Networks, 2023
Brain-Inspired Spiking Neural Network for Online Unsupervised Time Series Prediction.
Proceedings of the International Joint Conference on Neural Networks, 2023
SNATCH: Stealing Neural Network Architecture from ML Accelerator in Intelligent Sensors.
Proceedings of the 2023 IEEE SENSORS, Vienna, Austria, October 29 - Nov. 1, 2023, 2023
Proceedings of the 2023 IEEE SENSORS, Vienna, Austria, October 29 - Nov. 1, 2023, 2023
Proceedings of the Eleventh International Conference on Learning Representations, 2023
Associative Memory Augmented Asynchronous Spatiotemporal Representation Learning for Event-based Perception.
Proceedings of the Eleventh International Conference on Learning Representations, 2023
Heterogeneous Neuronal and Synaptic Dynamics for Spike-Efficient Unsupervised Learning: Theory and Design Principles.
Proceedings of the Eleventh International Conference on Learning Representations, 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Brain-Inspired Spatiotemporal Processing Algorithms for Efficient Event-Based Perception.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Task-Driven RGB-Lidar Fusion for Object Tracking in Resource-Efficient Autonomous System.
IEEE Trans. Intell. Veh., 2022
IEEE Trans. Ind. Electron., 2022
Robust Processing-In-Memory With Multibit ReRAM Using Hessian-Driven Mixed-Precision Computation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process.
ACM J. Emerg. Technol. Comput. Syst., 2022
CoRR, 2022
Forecasting local behavior of multi-agent system and its application to forest fire model.
CoRR, 2022
An Algorithm-Hardware Co-design Framework to Overcome Imperfections of Mixed-signal DNN Accelerators.
CoRR, 2022
XMD: An Expansive Hardware-telemetry based Malware Detector to enhance Endpoint Detection.
CoRR, 2022
RADNet: A Deep Neural Network Model for Robust Perception in Moving Autonomous Systems.
CoRR, 2022
Unraveled Multilevel Transformation Networks for Predicting Sparsely-Observed Spatiotemporal Dynamics.
CoRR, 2022
IEEE Access, 2022
Analysis of the Effect of Hot Carrier Injection in An Integrated Inductive Voltage Regulator.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
A Methodology for Understanding the Origins of False Negatives in DNN Based Object Detectors.
Proceedings of the International Joint Conference on Neural Networks, 2022
Proceedings of the International Joint Conference on Neural Networks, 2022
Proceedings of the International Joint Conference on Neural Networks, 2022
Proceedings of the International Joint Conference on Neural Networks, 2022
Proceedings of the International Joint Conference on Neural Networks, 2022
Sequence Approximation using Feedforward Spiking Neural Network for Spatiotemporal Learning: Theory and Optimization Methods.
Proceedings of the Tenth International Conference on Learning Representations, 2022
2021
MAHASIM: Machine-Learning Hardware Acceleration Using a Software-Defined Intelligent Memory System.
J. Signal Process. Syst., 2021
IEEE Trans. Image Process., 2021
Machine Learning in Wavelet Domain for Electromagnetic Emission Based Malware Analysis.
IEEE Trans. Inf. Forensics Secur., 2021
Pattern Recognit., 2021
Physics-incorporated convolutional recurrent neural networks for source identification and forecasting of dynamical systems.
Neural Networks, 2021
IEEE Internet Things J., 2021
Genetic Algorithm-Based Energy-Aware CNN Quantization for Processing-In-Memory Architecture.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Characterization of Generalizability of Spike Time Dependent Plasticity trained Spiking Neural Networks.
CoRR, 2021
CoRR, 2021
A Deep Learning Approach for Predicting Spatiotemporal Dynamics From Sparsely Observed Data.
IEEE Access, 2021
Proceedings of the 13th International Conference on Computer and Automation Engineering, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Towards Improving the Trustworthiness of Hardware based Malware Detector using Online Uncertainty Estimation.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the 17th IEEE International Conference on Advanced Video and Signal Based Surveillance, 2021
Characterization of Drain Current Variations in FeFETs for PIM-based DNN Accelerators.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
Low Power Unsupervised Anomaly Detection by Nonparametric Modeling of Sensor Statistics.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse.
IEEE Trans. Very Large Scale Integr. Syst., 2020
An Inductive Voltage Regulator With Overdrive Tracking Across Input Voltage in Cascoded Power Stage.
IEEE Trans. Circuits Syst., 2020
Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO.
IEEE J. Solid State Circuits, 2020
Attention-Based Activation Pruning to Reduce Data Movement in Real-Time AI: A Case-Study on Local Motion Planning in Autonomous Vehicles.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
Cross-Layer Noise Analysis in Smart Digital Pixel Sensors With Integrated Deep Neural Network.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
A Deep Learning-based Collocation Method for Modeling Unknown PDEs from Sparse Observation.
CoRR, 2020
PhICNet: Physics-Incorporated Convolutional Recurrent Neural Networks for Modeling Dynamical Systems.
CoRR, 2020
Low Power Unsupervised Anomaly Detection by Non-Parametric Modeling of Sensor Statistics.
CoRR, 2020
BiasP: a DVFS based exploit to undermine resource allocation fairness in linux platforms.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
SAFE-DNN: A Deep Neural Network With Spike Assisted Feature Extraction For Noise Robust Inference.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Flex-PIM: A Ferroelectric FET based Vector Matrix Multiplication Engine with Dynamical Bitwidth and Floating Point Precision.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Proceedings of the 2020 IEEE Sensors, Rotterdam, The Netherlands, October 25-28, 2020, 2020
Uncertainty Characterization in Active Sensor Systems with DNN-based Feedback Control.
Proceedings of the 2020 IEEE Sensors, Rotterdam, The Netherlands, October 25-28, 2020, 2020
Proceedings of the 2020 IEEE International Conference on Robotics and Automation, 2020
Silicon vs. Organic Interposer: PPA and Reliability Tradeoffs in Heterogeneous 2.5D Chiplet Integration.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Q-PIM: A Genetic Algorithm based Flexible DNN Quantization Method and Application to Processing-In-Memory Platform.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
WarningNet: A Deep Learning Platform for Early Warning of Task Failures under Input Perturbation for Reliable Autonomous Platforms.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
A Configurable Dual-Mode PRINCE Cipher with Security Aware Pipelining in 65nm for High Throughput Applications.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
A Fully Synthesized Integrated Buck Regulator with Auto-generated GDS-II in 65nm CMOS Process.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
Effect of Process Variations in Digital Pixel Circuits on the Accuracy of DNN based Smart Sensor.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
Autotuning of Integrated Inductive Voltage Regulator Using On-Chip Delay Sensor to Tolerate Process and Passive Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Design and Analysis of a Neural Network Inference Engine Based on Adaptive Weight Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering.
IEEE J. Solid State Circuits, 2019
IEEE Internet Things J., 2019
Multigated Carbon Nanotube Field Effect Transistors-Based Physically Unclonable Functions As Security Keys.
IEEE Internet Things J., 2019
IBM J. Res. Dev., 2019
CAMEL: An Adaptive Camera With Embedded Machine Learning-Based Sensor Parameter Control.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Automatic GDSII Generator for On-Chip Voltage Regulator for Easy Integration in Digital SoCs.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
On the Effect of NBTI Induced Aging of Power Stage on the Transient Performance of On-Chip Voltage Regulators.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Improving Robustness of ReRAM-based Spiking Neural Network Accelerator with Stochastic Spike-timing-dependent-plasticity.
Proceedings of the International Joint Conference on Neural Networks, 2019
Mixture of Pre-processing Experts Model for Noise Robust Deep Learning on Resource Constrained Platforms.
Proceedings of the International Joint Conference on Neural Networks, 2019
Proceedings of the International Joint Conference on Neural Networks, 2019
Proceedings of the International Joint Conference on Neural Networks, 2019
A Spectral Convolutional Net for Co-Optimization of Integrated Voltage Regulators and Embedded Inductors.
Proceedings of the International Conference on Computer-Aided Design, 2019
Extracting Side-Channel Leakage from Round Unrolled Implementations of Lightweight Ciphers.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
Mitigating Power Supply Glitch based Fault Attacks with Fast All-Digital Clock Modulation Circuit.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 30th British Machine Vision Conference 2019, 2019
Proceedings of the 30th British Machine Vision Conference 2019, 2019
2018
J. Signal Process. Syst., 2018
ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator.
IEEE J. Solid State Circuits, 2018
An Energy-Quality Scalable Wireless Image Sensor Node for Object-Based Video Surveillance.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
CoRR, 2018
Blindsight: Blinding EM Side-Channel Leakage using Built-In Fully Integrated Inductive Voltage Regulator.
CoRR, 2018
Proceedings of the 6th International Conference on Learning Representations, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
An Unsupervised Anomalous Event Detection Framework with Class Aware Source Separation.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018
Energy efficient and side-channel secure hardware architecture for lightweight cipher SIMON.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Accelerating biophysical neural network simulation with region of interest based approximation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Performance based tuning of an inductive integrated voltage regulator driving a digital core against process and passive variations.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Edge-cloud collaborative processing for intelligent internet of things: a case study on smart surveillance.
Proceedings of the 55th Annual Design Automation Conference, 2018
HybridNet: Integrating Model-based and Data-driven Learning to Predict Evolution of Dynamical Systems.
Proceedings of the 2nd Annual Conference on Robot Learning, 2018
Adaptive Control of Camera Modality with Deep Neural Network-Based Feedback for Efficient Object Tracking.
Proceedings of the 15th IEEE International Conference on Advanced Video and Signal Based Surveillance, 2018
Edge-Host Partitioning of Deep Neural Networks with Feature Space Encoding for Resource-Constrained Internet-of-Things Platforms.
Proceedings of the 15th IEEE International Conference on Advanced Video and Signal Based Surveillance, 2018
2017
A Power-Aware Digital Multilayer Perceptron Accelerator with On-Chip Training Based on Approximate Computing.
IEEE Trans. Emerg. Top. Comput., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
An All-Digital Fully Integrated Inductive Buck Regulator With A 250-MHz Multi-Sampled Compensator and a Lightweight Auto-Tuner in 130-nm CMOS.
IEEE J. Solid State Circuits, 2017
Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators.
J. Hardw. Syst. Secur., 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Invited paper: Low power requirements and side-channel protection of encryption engines: Challenges and opportunities.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017
Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Design of an Energy-Efficient Accelerator for Training of Convolutional Neural Networks using Frequency-Domain Computation.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
Partitioning Methods for Interface Circuit of Heterogeneous 3-D-ICs Under Process Variation.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Impact of Heterogeneous Technology Integration on the Power, Performance, and Quality of a 3D Image Sensor.
IEEE Trans. Multi Scale Comput. Syst., 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
IEEE Comput. Archit. Lett., 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Speeding up Convolutional Neural Network Training with Dynamic Precision Scaling and Flexible Multiplier-Accumulator.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Dynamic Approximation with Feedback Control for Energy-Efficient Recurrent Neural Network Hardware.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
An Energy-Aware Approach to Noise-Robust Moving Object Detection for Low-Power Wireless Image Sensor Platforms.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
Integrated all-digital low-dropout regulator as a countermeasure to power attack in encryption engines.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016
An integrated inductive VR with a 250MHz all-digital multisampled compensator and on-chip auto-tuning of coefficients in 130nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Reconfigurable 96×128 active pixel sensor with 2.1µW/mm<sup>2</sup> power generation and regulated multi-domain power delivery for self-powered imaging.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Behavioral modeling of timing slack variation in digital circuits due to power supply noise.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
An energy-efficient wireless video sensor node with a region-of-interest based multi-parameter rate controller for moving object surveillance.
Proceedings of the 13th IEEE International Conference on Advanced Video and Signal Based Surveillance, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEEE Trans. Multi Scale Comput. Syst., 2015
A Memory-Based Logic Block With Optimized-for-Read SRAM for Energy-Efficient Reconfigurable Computing Fabric.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
On the Impact of Energy-Accuracy Tradeoff in a Digital Cellular Neural Network for Image Processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
Architectural Reliability: Lifetime Reliability Characterization and Management ofMany-Core Processors.
IEEE Comput. Archit. Lett., 2015
Near Data Processing: Impact and Optimization of 3D Memory System Architecture on the Uncore.
Proceedings of the 2015 International Symposium on Memory Systems, 2015
Experimental characterization of in-package microfluidic cooling on a System-on-Chip.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Exploring power attack protection of resource constrained encryption engines using integrated low-drop-out regulators.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
A power-aware digital feedforward neural network platform with backpropagation driven approximate synapses.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
2014
A Variation-Aware Preferential Design Approach for Memory-Based Reconfigurable Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Control Principles and On-Chip Circuits for Active Cooling Using Integrated Superlattice-Based Thin-Film Thermoelectric Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Resilient Pipeline Under Supply Noise With Programmable Time Borrowing and Delayed Clock Gating.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A Dynamic Timing Error Prevention Technique in Pipelines With Time Borrowing and Clock Stretching.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
An analytical approach to system-level variation analysis and optimization for multi-core processor.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Energy Introspector: A parallel, composable framework for integrated power-reliability-thermal modeling for multicore architectures.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014
Impact of process variation in inductive integrated voltage regulator on delay and power of digital circuits.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
An on-chip autonomous thermoelectric energy management system for energy-efficient active cooling.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Robust low-power reconfigurable computing with a variation-aware preferential design approach.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
On the Design of Reliable 3D-ICs Considering Charged Device Model ESD Events During Die Stacking.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Proceedings of the 9th Workshop on Embedded Systems Security, 2014
2013
ACM J. Emerg. Technol. Comput. Syst., 2013
On the impact of 3D integration on high-throughput sensor information processing: A case study with image sensing.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the IEEE Frontiers in Education Conference, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Exploring tunnel-FET for ultra low power analog applications: a case study on operational transconductance amplifier.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
On the potential of 3D integration of inductive DC-DC converter for high-performance power delivery.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
A 110nA synchronous boost regulator with autonomous bias gating for energy harvesting.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
All-Digital Adaptive Clocking to Tolerate Transient Supply Noise in a Low-Voltage Operation.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Modeling and Designing for Accuracy and Energy Efficiency in Wireless Electroencephalography Systems.
ACM J. Emerg. Technol. Comput. Syst., 2012
Improving IC Security Against Trojan Attacks Through Integration of Security Monitors.
IEEE Des. Test Comput., 2012
On the parametric failures of SRAM in a 3D-die stack considering tier-to-tier supply cross-talk.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Self-adaptive power gating with test circuit for on-line characterization of energy inflection activity.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Instruction-based energy estimation methodology for asymmetric manycore processor simulations.
Proceedings of the International ICST Conference on Simulation Tools and Techniques, 2012
Low-power design under variation using error prevention and error tolerance (invited paper).
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Tier-adaptive-voltage-scaling (TAVS): A methodology for post-silicon tuning of 3D ICs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Prospects of active cooling with integrated super-lattice based thin-film thermoelectric devices for mitigating hotspot challenges in microprocessors.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Reconfigurable SRAM Architecture With Spatial Voltage Scaling for Low Power Mobile Multimedia Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2011
A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Modeling and Analysis of Image Dependence and Its Implications for Energy Savings in Error Tolerant Image Processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Low energy process variation tolerant digital image processing system design based on accuracy-energy tradeoffs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Dual-Source-Line-Bias Scheme to Improve the Read Margin and Sensing Accuracy of STTRAM in Sub-90-nm Nodes.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEEE Des. Test Comput., 2010
Optimization of burn-in test for many-core processors through adaptive spatiotemporal power migration.
Proceedings of the 2011 IEEE International Test Conference, 2010
A low power system with adaptive data compression for wireless monitoring of physiological signals and its application to wireless electroencephalography.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Signal processing methods and hardware-structure for on-line characterization of thermal gradients in many-core processors.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics.
IEEE J. Solid State Circuits, 2009
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs.
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Experimental analysis of sequence dependence on energy saving for error tolerant image processing.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the 27th International Conference on Computer Design, 2009
A circuit-software co-design approach for improving EDP in reconfigurable frameworks.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applications.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process.
IEEE J. Solid State Circuits, 2008
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield.
Proceedings of the 26th International Conference on Computer Design, 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Analysis of the impact of interfacial oxide thickness variation on metal-gate high-K circuits.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices.
Microelectron. J., 2007
Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS.
IEEE J. Solid State Circuits, 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
2006
A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET.
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM.
Proceedings of the 43rd Design Automation Conference, 2006
SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Optimization of Surface Orientation for High-Performance, Low-Power and Robust FinFET SRAM.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations.
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits.
IEEE J. Solid State Circuits, 2005
Process variation in embedded memories: failure analysis and variation aware architecture.
IEEE J. Solid State Circuits, 2005
Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits.
Proceedings of the 2005 Design, 2005
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies.
Proceedings of the 2005 Design, 2005
Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Modeling and optimization approach to robust and low-power FinFET SRAM design in nanoscale era.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
Proceedings of the 41th Design Automation Conference, 2004
Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits.
Proc. IEEE, 2003
Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
A forward body-biased low-leakage SRAM cache: device and architecture considerations.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling.
Proceedings of the 40th Design Automation Conference, 2003
2002