Harsh Sohal

Orcid: 0000-0002-3123-7284

According to our database1, Harsh Sohal authored at least 6 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Power-Area-Optimized Approximate Multiplier Design for Image Fusion.
Circuits Syst. Signal Process., April, 2024

2021
A novel parallel prefix adder for optimized Radix-2 FFT processor.
Multidimens. Syst. Signal Process., 2021

A Novel ASIC-Based Variable Latency Speculative Parallel Prefix Adder for Image Processing Application.
Circuits Syst. Signal Process., 2021

2020
Statistical Analysis of HRV Parameters for the Detection of Arrhythmia.
Int. J. Image Graph., 2020

2019
Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design.
J. Circuits Syst. Comput., 2019

2014
Multi-Frequency Electrical Impedance Tomography System With Automatic Self-Calibration for Long-Term Monitoring.
IEEE Trans. Biomed. Circuits Syst., 2014


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