Hideo Yamasaki

According to our database, Hideo Yamasaki authored at least 4 papers between 2003 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2007

A Real-Time Image-Feature-Extraction and Vector-Generation VLSI Employing Arrayed-Shift-Register Architecture.

Hideo Yamasaki, Tadashi Shibata

IEEE J. Solid State Circuits, 2007

2005

A high-speed median filter VLSI using floating-gate-MOS-based low-power majority voting circuits.

Hideo Yamasaki, Tadashi Shibata

Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004

A real-time VLSI median filter employing two-dimensional bit-propagating architecture.

Hideo Yamasaki, Tadashi Shibata

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

A Mixed-Signal VLSI for Real-Time Generation of Edge-Based Image Vectors.

Masakazu Yagi, Hideo Yamasaki, Tadashi Shibata

Proceedings of the Advances in Neural Information Processing Systems 16 [Neural Information Processing Systems, 2003