Hikaru Takayashiki

Orcid: 0000-0003-0010-1672

According to our database¹, Hikaru Takayashiki authored at least 8 papers between 2019 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

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2024

Performance Analysis of the NICAM Benchmark on MN-Core Processor.

[BibT_eX]

[DOI]

Proceedings of the SC24-W: Workshops of the International Conference for High Performance Computing, 2024

2023

A New Sparse GEneral Matrix-matrix Multiplication Method for Long Vector Architecture by Hierarchical Row Merging.

[BibT_eX]

[DOI]

Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

2022

Page-Address Coalescing of Vector Gather Instructions for Efficient Address Translation.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE/ACM Workshop on Irregular Applications: Architectures and Algorithms, 2022

2021

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021

A Metadata Prefetching Mechanism for Hybrid Memory Architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2021

2019

A Skewed Multi-banked Cache for Many-core Vector Processors.

[BibT_eX]

[DOI]

Supercomput. Front. Innov., 2019

An Energy-aware Dynamic Data Allocation Mechanism for Many-channel Memory Systems.

[BibT_eX]

[DOI]

Supercomput. Front. Innov., 2019

A Hardware Prefetching Mechanism for Vector Gather Instructions.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE/ACM Workshop on Irregular Applications: Architectures and Algorithms, 2019

Hikaru Takayashiki

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