Hiroshi Nakada

According to our database1, Hiroshi Nakada authored at least 20 papers between 1987 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2012
Survey of RFID and Its Application to International Ocean/Air Container Tracking.
IEICE Trans. Commun., 2012

2004
Dynamically Reconfigurable Logic LSI: PCA-2.
IEICE Trans. Inf. Syst., 2004

2002
A Method of Mapping Finite State Machine into PCA Plastic Parts.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2001
Self-reorganising systems on VLSI circuits.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001

2000
An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture.
Proceedings of the Field-Programmable Logic and Applications, 2000

Communicating logic: an alternative embedded stream processing paradigm.
Proceedings of ASP-DAC 2000, 2000

1999
Plastic Cell Architecture: A Dynamically Reconfigurable Hardware-Based Computer.
Proceedings of the Parallel and Distributed Processing, 1999

1997
A New Processor Architecture for Digital Signal Transport Systems.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1995
Performance improvement technique for synchronous circuits realized as LUT-based FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 1995

Telecommunication-Oriented FPGA and Dedicated CAD System.
Proceedings of the Field-Programmable Logic and Applications, 5th International Workshop, 1995

1994
PROTEUS: Programmable Hardware for Telecommunication Systems.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

A Speed-Up Technique for Synchronous Circuits Realized as LUT-Based FPGAs.
Proceedings of the Field-Programmable Logic, 1994

1992
A 12.8 GFLOPS multi-DSP system for super high definition image processing.
Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

New Application of FPLs to Programmable Digital Communication Cirucits.
Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992

1990
Variable rate speech coding for asynchronous transfer mode.
IEEE Trans. Commun., 1990

Design of a d-connected digraph with a minimum number of edges and a quasiminimal diameter.
Discret. Appl. Math., 1990

Vector processor design for parallel DSP systems using hierarchical behavioral description based synthesizer.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1988
Variable rate speech coding and network delay analysis for universal transport network.
Proceedings of the Seventh Annual Joint Conference of the IEEE Computer and Communcations Societies. Networks: Evolution or Revolution?, 1988

1987
Sufficient conditions for maximally connected dense graphs.
Discret. Math., 1987


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