Kiyoshi Oguri

According to our database1, Kiyoshi Oguri authored at least 76 papers between 1990 and 2019.

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Bibliography

2019
Pipelined FPGA Implementation of a Wave-Front-Fetch Graph Cut System.
Proceedings of the Complex, Intelligent, and Software Intensive Systems, 2019

2018
FPGA Implementation of a Real-Time Super-Resolution System Using Flips and an RNS-Based CNN.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

A new stereo formulation not using pixel and disparity models.
CoRR, 2018

An FPGA-oriented Graph Cut Algorithm for Accelerating Stereo Vision.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Discussion on High Level Synthesis FPGA Design of Camera Calibration.
Proceedings of the Complex, Intelligent, and Software Intensive Systems, 2018

2017
Deep-pipelined FPGA Implementation of Real-time Object Tracking using a Particle Filter.
Int. J. Netw. Comput., 2017

Comparative Evaluation of FPGA Implementation Alternatives for Real-Time Robust Ellipse Estimation based on RANSAC Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

FPGA Implementation of A Graph Cut Algorithm For Stereo Vision.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

FPGA implementation of a real-time super-resolution system with a CNN based on a residue number system.
Proceedings of the International Conference on Field Programmable Technology, 2017

Power Performance Analysis of FPGA-Based Particle Filtering for Realtime Object Tracking.
Proceedings of the Complex, Intelligent, and Software Intensive Systems, 2017

HLS-Based FPGA Acceleration of Building-Cube Stencil Computation.
Proceedings of the Complex, Intelligent, and Software Intensive Systems, 2017

2016
FPGA-based Real-Time Object Tracking Using a Particle Filter with Stream Architecture.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

FPGA implementation of a real-time super-resolution system using a convolutional neural network.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

A Comparison of Machine Learning Classifiers for FPGA Implementation of HOG-Based Human Detection.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015
Power Performance Profiling of 3-D Stencil Computation on an FPGA Accelerator for Efficient Pipeline Optimization.
SIGARCH Comput. Archit. News, 2015

Performance Modeling of Stencil Computing on a Stream-Based FPGA Accelerator for Efficient Design Space Exploration.
IEICE Trans. Inf. Syst., 2015

Study of mirror box therapy support system by leap motion.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2015

An energy-efficient FPGA-based soft-core processor with a configurable word size ECC arithmetic accelerator.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

2014
A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis.
SIGARCH Comput. Archit. News, 2014

A soft-core processor for finite field arithmetic with a variable word size accelerator.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

FPGA Implementation of a Video Based Abnormal Action Detection System with Real-Time Cubic Higher Order Local Auto-Correlation Analysis.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
FPGA Implementation of Human Detection by HOG Features with AdaBoost.
IEICE Trans. Inf. Syst., 2013

Performance modeling and optimization of 3-D stencil computation on a stream-based FPGA accelerator.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

A Fast Runtime Visualization of a GPU-Based 3D-FDTD Electromagnetic Simulation.
Proceedings of the First International Symposium on Computing and Networking, 2013

2012
Performance comparison of GPU programming frameworks with the striped Smith-Waterman algorithm.
SIGARCH Comput. Archit. News, 2012

Implementation of a GPU-Oriented Absorbing Boundary Condition for 3D-FDTD Electromagnetic Simulation.
IEICE Trans. Inf. Syst., 2012

Deep-pipelined FPGA implementation of ellipse estimation for eye tracking.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
A discussion on calculating eigenvalues of real symmetric tridiagonal matrices on a GPU.
SIGARCH Comput. Archit. News, 2011

GPU implementation and optimization of electromagnetic simulation using the FDTD method for antenna designing.
SIGARCH Comput. Archit. News, 2011

Steering Time-Dependent Estimation of Posteriors with Hyperparameter Indexing in Bayesian Topic Models.
Proceedings of the Advances in Knowledge Discovery and Data Mining, 2011

Clustering Documents with Maximal Substrings.
Proceedings of the Enterprise Information Systems - 13th International Conference, 2011

Documents as a Bag of Maximal Substrings - An Unsupervised Feature Extraction for Document Clustering.
Proceedings of the ICEIS 2011, 2011

Semi-supervised Bibliographic Element Segmentation with Latent Permutations.
Proceedings of the Digital Libraries: For Cultural Heritage, Knowledge Dissemination, and Future Creation, 2011

Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010
Implementation of a programming environment with a multithread model for reconfigurable systems.
SIGARCH Comput. Archit. News, 2010

Automatic Pipeline Construction Focused on Similarity of Rate Law Functions for an FPGA-based Biochemical Simulator.
IPSJ Trans. Syst. LSI Des. Methodol., 2010

Unsupervised Segmentation of Bibliographic Elements with Latent Permutations.
Proceedings of the Web Information Systems Engineering - WISE 2010 Workshops, 2010

Modeling Topical Trends over Continuous Time with Priors.
Proceedings of the Advances in Neural Networks, 2010

A datapath classification method for FPGA-based scientific application accelerator systems.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Infinite latent process decomposition.
Proceedings of the 2010 IEEE International Conference on Bioinformatics and Biomedicine Workshops, 2010

2009
A novel multiple-walk parallel algorithm for the Barnes-Hut treecode on GPUs - towards cost effective, high performance N-body simulation.
Comput. Sci. Res. Dev., 2009

Bag of Timestamps: A Simple and Efficient Bayesian Chronological Mining.
Proceedings of the Advances in Data and Web Management, Joint International Conferences, 2009

A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Accelerating Collapsed Variational Bayesian Inference for Latent Dirichlet Allocation with Nvidia CUDA Compatible Devices.
Proceedings of the Next-Generation Applied Intelligence, 2009

Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Dynamic hyperparameter optimization for bayesian topical trend analysis.
Proceedings of the 18th ACM Conference on Information and Knowledge Management, 2009

Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator.
Proceedings of the Reconfigurable Computing: Architectures, 2009

Accelerating Phase Correlation Functions Using GPU and FPGA.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

Bayesian Multi-topic Microarray Analysis with Hyperparameter Reestimation.
Proceedings of the Advanced Data Mining and Applications, 5th International Conference, 2009

2008
An optimization method of DMA transfer for a general purpose reconfigurable machine.
Proceedings of the FPL 2008, 2008

Retrieving 3-d information with FPGA-based stream processing.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

2007
An optimization method focusing on fixed-point arithmetic in applications for dynamically reconfigurable processor.
Syst. Comput. Jpn., 2007

FPGA Implementation of a Statically Reconfigurable Java Environment for Embedded Systems.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator.
Proceedings of the FPL 2007, 2007

Implementation of a barotropic operator for ocean model simulation using a reconfigurable machine.
Proceedings of the FPL 2007, 2007

2006
An Implementation Technique of Multi-Cycled Arithmetic Functions For a Dynamically Reconfigurable Processor.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

New Area Management Method Based on "Pressure" for Plastic Cell Architecture.
Proceedings of the Embedded and Ubiquitous Computing, 2005

Evaluation of Space Allocation Circuits.
Proceedings of the Embedded and Ubiquitous Computing, 2005

2004
Implementation of the Extended Euclidean Algorithm for the Tate Pairing on FPGA.
Proceedings of the Field Programmable Logic and Application, 2004

2003
Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA.
Proceedings of the Advances in Computer Systems Architecture, 2003

2002
A Method of Mapping Finite State Machine into PCA Plastic Parts.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2001
Self-reorganising systems on VLSI circuits.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001

2000
An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture.
Proceedings of the Field-Programmable Logic and Applications, 2000

Communicating logic: an alternative embedded stream processing paradigm.
Proceedings of ASP-DAC 2000, 2000

1999
Plastic Cell Architecture: A Dynamically Reconfigurable Hardware-Based Computer.
Proceedings of the Parallel and Distributed Processing, 1999

1998
Message routing latency-minimizing method in an ASIC design for distributed cooperative communication protocol processing.
Syst. Comput. Jpn., 1998

The Plastic Cell Architecture for Dynamic Reconfigurable Computing.
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

General-Purpose Computer Architecture Based on Fully Programmable Logic.
Proceedings of the Evolvable Systems: From Biology to Hardware, 1998

A Hardware Implementation of Constraint Satisfaction Problem Based on New Reconfigurable LSI Architecture.
Proceedings of the Field-Programmable Logic and Applications, 1998

Plastic Cell Architecture: Towards Reconfigurable Computing for General-Purpose.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1995
Test Synthesis from Behavioral Description Based on Data Transfer Analysis.
IEICE Trans. Inf. Syst., 1995

1990
Vector processor design for parallel DSP systems using hierarchical behavioral description based synthesizer.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Multi-Level Optimization for Large Scale ASICS.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990


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