Ho Fai Ko

According to our database, Ho Fai Ko authored at least 19 papers between 2004 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation.

Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging.

Ho Fai Ko, Nicola Nicolici

IEEE Trans. Computers, 2012

In-system constrained-random stimuli generation for post-silicon validation.

Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici

Proceedings of the 2012 IEEE International Test Conference, 2012

2011

Design-for-Debug Architecture for Distributed Embedded Logic Analysis.

Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici

IEEE Trans. Very Large Scale Integr. Syst., 2011

2010

Automated trace signals selection using the RTL descriptions.

Ho Fai Ko, Nicola Nicolici

Proceedings of the 2011 IEEE International Test Conference, 2010

Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging.

Ho Fai Ko, Nicola Nicolici

Proceedings of the 15th European Test Symposium, 2010

2009

Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug.

Ho Fai Ko, Nicola Nicolici

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Design-for-debug for post-silicon validation: Can high-level descriptions help?

Nicola Nicolici, Ho Fai Ko

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

Resource-Efficient Programmable Trigger Units for Post-Silicon Validation.

Ho Fai Ko, Nicola Nicolici

Proceedings of the 14th IEEE European Test Symposium, 2009

2008

Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test.

Ho Fai Ko, Nicola Nicolici

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy.

Ho Fai Ko, Nicola Nicolici

J. Electron. Test., 2008

Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs.

Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici

Proceedings of the 2008 IEEE International Test Conference, 2008

A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test.

Ho Fai Ko, Nicola Nicolici

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

On Automated Trigger Event Generation in Post-Silicon Validation.

Ho Fai Ko, Nicola Nicolici

Proceedings of the Design, Automation and Test in Europe, 2008

Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation.

Ho Fai Ko, Nicola Nicolici

Proceedings of the Design, Automation and Test in Europe, 2008

2006

RTL Scan Design for Skewed-Load At-speed Test under Power Constraints.

Ho Fai Ko, Nicola Nicolici

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2005

Register-transfer level functional scan for hierarchical designs.

Ho Fai Ko, Qiang Xu, Nicola Nicolici

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Functional Illinois Scan Design at RTL.

Ho Fai Ko, Nicola Nicolici

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing.

Ho Fai Ko, Nicola Nicolici

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004