Ho-Yin Chen

According to our database, Ho-Yin Chen authored at least 1 paper in 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns.

Nicky Lu, Chun Shiah, Juang-Ying Chueh, Bor-Doou Rong, Wei-Jr Huang, Ho-Yin Chen, Cheng-Nan Chang, Chia-Wei Chang, Tzung-Shen Chen

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021