Hongyi Lu

Orcid: 0000-0002-6864-5409

According to our database1, Hongyi Lu authored at least 23 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
MOAT: Towards Safe BPF Kernel Extension.
CoRR, 2023

RingGuard: Guard io_uring with eBPF.
Proceedings of the 1st Workshop on eBPF and Kernel Extensions, 2023

2022
A Novel Faster All-Pair Shortest Path Algorithm Based on the Matrix Multiplication for GPUs.
CoRR, 2022

Raven: a novel kernel debugging tool on RISC-V.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
BADUSB-C: Revisiting BadUSB with Type-C.
Proceedings of the IEEE Security and Privacy Workshops, 2021

A Novel Memory Management for RISC-V Enclaves.
Proceedings of the HASP '21: Workshop on Hardware and Architectural Support for Security and Privacy, 2021

A Memory Saving Mechanism Based on Data Transferring for Pipeline Parallelism.
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021

Co-designing the Topology/Algorithm to Accelerate Distributed Training.
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021

2018
Adaptive VC Partitioning for NoCs in GPGPUs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2015
Adaptive remaining hop count flow control: Consider the interaction between packets.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
A comprehensive comparison between virtual cut-through and wormhole routers for cache coherent Network on-Chips.
IEICE Electron. Express, 2014

2012
The Design of Experimental Nodes on Teaching Platform of Cloud Laboratory (TPCL).
Proceedings of the Computer Applications for Database, Education, and Ubiquitous Computing, 2012

2011
A specialized low-cost vectorized loop buffer for embedded processors.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
DSS: Applying asynchronous techniques to architectures exploiting ILP at compile time.
Proceedings of the 28th International Conference on Computer Design, 2010

2009
Using Pcache to Speedup Interpretation in Dynamic Binary Translation.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2009

A Light-weight Code Cache Design for Dynamic Binary Translation.
Proceedings of the 15th IEEE International Conference on Parallel and Distributed Systems, 2009

A Hardware Approach for Reducing Interpretation Overhead.
Proceedings of the Ninth IEEE International Conference on Computer and Information Technology, 2009

2008
A Novel Hardware Assisted Full Virtualization Technique.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008

DBTIM: An Advanced Hardware Assisted Full Virtualization Architecture.
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers.
Proceedings of the 45th Design Automation Conference, 2008

2006
A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor Using WDDL and Wave-Pipelining.
Proceedings of the Information Security and Cryptology, Second SKLOIS Conference, 2006

2004
TengYue-1TengYue: In Chinese means jump over.: A High Performance Embedded SoC.
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004


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