Hooman Nabovati

According to our database1, Hooman Nabovati authored at least 17 papers between 2009 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2013
Highly linear low voltage low power CMOS LNA.
IEICE Electron. Express, 2013

A new g<sub>m</sub>-boosting current reuse CMOS folded cascode LNA.
IEICE Electron. Express, 2013

2012
New linearization method for low voltage, low power folded cascode LNAs.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Design of 0.5V, 1.28mW CMOS UWB mixer using the body effect.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Design of 0.4V, 386nW OTA using DTMOS technique for biomedical applications.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Gain increasing techniques for CMOS folded cascode LNAs at low voltage and low power operations.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Design of 0.45V, 1.3mW ultra high gain CMOS LNA using gm-boosting and forward body biasing technique.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

An ultra low voltage ultra low power CMOS UWB LNA using forward body biasing.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Accurate modeling of low actuation voltage RFMEMS switches using artificial neural networks.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Developing a new phase noise estimation technique based on time varying model.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Ultra-low power self-calibrating process-insensitive BPSK demodulator for bio-implantable chips.
IEICE Electron. Express, 2011

Design of high gain CMOS LNA with improved linearity using modified derivative superposition.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Design of new full adder cell using hybrid-CMOS logic style.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Design of a high efficient fully integrated CMOS rectifier using bootstrapped technique for sub-micron and wirelessly powered applications.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Design of low voltage low power dual-band LNA with forward body biasing technique.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
A 5.7GHz low noise figure ultra high gain CMOS LNA with inter stage technique.
IEICE Electron. Express, 2010

2009
New geometry for improving Q-factor of spiral integrated inductor on low cost integrated circuit process.
Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009


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