Ehsan Kargaran

According to our database1, Ehsan Kargaran authored at least 22 papers between 2009 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
A 1.5-2.8 GHz current-mode LNTA achieving >25 dBm IIP3 and +8 dBm P-1dB gain compression.
Microelectron. J., 2019

A Sub-0.6V, 330 µW, 0.15 mm<sup>2</sup> Receiver Front-End for Bluetooth Low Energy (BLE) in 22 nm FD-SOI with Zero External Components.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
Design and Analysis of 2.4 GHz 30~µW CMOS LNAs for Wearable WSN Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

An FDD Wireless Diversity Receiver With Transmitter Leakage Cancellation in Transmit and Receive Bands.
IEEE J. Solid State Circuits, 2018

A Sub-IV, 72 μW Stacked LNA-VCO for Wireless Sensor Network Applications.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

A Sub-1V, 220 μW Receiver Frontend for Wearable Wireless Sensor Network Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A 30μW, 3.3dB NF CMOS LNA for wearable WSN applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2013
An ultra low power OTA with improved unity gain bandwidth product.
IEICE Electron. Express, 2013

Highly linear low voltage low power CMOS LNA.
IEICE Electron. Express, 2013

A new g<sub>m</sub>-boosting current reuse CMOS folded cascode LNA.
IEICE Electron. Express, 2013

2012
New linearization method for low voltage, low power folded cascode LNAs.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Design of 0.5V, 1.28mW CMOS UWB mixer using the body effect.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Design of 0.4V, 386nW OTA using DTMOS technique for biomedical applications.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Gain increasing techniques for CMOS folded cascode LNAs at low voltage and low power operations.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Design of 0.45V, 1.3mW ultra high gain CMOS LNA using gm-boosting and forward body biasing technique.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

An ultra low voltage ultra low power CMOS UWB LNA using forward body biasing.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Developing a new phase noise estimation technique based on time varying model.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Design of high gain CMOS LNA with improved linearity using modified derivative superposition.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Design of new full adder cell using hybrid-CMOS logic style.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Design of low voltage low power dual-band LNA with forward body biasing technique.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
A 5.7GHz low noise figure ultra high gain CMOS LNA with inter stage technique.
IEICE Electron. Express, 2010

2009
A low power ultra-wideband CMOS LNA with inter stage technique.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009


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