Howard M. Shao

According to our database1, Howard M. Shao authored at least 8 papers between 1983 and 1988.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

1988
A Pipeline Design of a Fast Prime Factor DFT on a Finite Field.
IEEE Trans. Computers, 1988

On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays.
IEEE Trans. Computers, 1988

1986
A single chip VLSI Reed-Solomon decoder.
Proceedings of the IEEE International Conference on Acoustics, 1986

1985
The VLSI design of a single chip for the multiplication of integers modulo a Fermat number.
IEEE Trans. Acoust. Speech Signal Process., 1985

VLSI Architectures for Computing Multiplications and Inverses in <i>GF</i>(2<sup><i>m</i></sup>).
IEEE Trans. Computers, 1985

A VLSI Design of a Pipeline Reed-Solomon Decoder.
IEEE Trans. Computers, 1985

VLSI residue multiplier modulo a Fermat number.
Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985

1983
A Parallel Architecture for Digital Filtering Using Fermat Number Transforms.
IEEE Trans. Computers, 1983


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