Hsin-Ming Wu

According to our database, Hsin-Ming Wu authored at least 3 papers between 2006 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2015

A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling.

Jung-Mao Lin, Ching-Yuan Yang, Hsin-Ming Wu

IEEE Trans. Very Large Scale Integr. Syst., 2015

2011

A 0.5/0.8-V 9-GHz Frequency Synthesizer With Doubling Generation in 0.13-μm CMOS.

Ching-Yuan Yang, Chih-Hsiang Chang, Jun-Hong Weng, Hsin-Ming Wu

IEEE Trans. Circuits Syst. II Express Briefs, 2011

2006

A 3.125-GHz Limiting Amplifier for Optical Receiver System.

Hsin-Ming Wu, Ching-Yuan Yang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006