Huqi Xiang

According to our database, Huqi Xiang authored at least 4 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

HFMLLR: Heterogeneous Feature Mining for Low-Overhead Latency Reduction Scheme of LDPC Codes in 3-D TLC nand Flash Memory.

Yongchao Wang, Debao Wei, Dixin Ma, Huqi Xiang, Liyan Qiao

IEEE Trans. Very Large Scale Integr. Syst., March, 2026

2025

Iteration and SDA-Driven LDPC Decoding Latency Reduction for 3-D TLC NAND Flash Memory.

Debao Wei, Yongchao Wang, Dejun Zhang, Huqi Xiang, Liyan Qiao

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2025

LVDE: A Lightweight Threshold Voltage Distribution Estimation Strategy for High-Performance 3-D Nand Flash Memory.

Zhelong Piao, Debao Wei, Huqi Xiang, Liyan Qiao, Xiyuan Peng

IEEE Trans. Circuits Syst. I Regul. Pap., September, 2025

2024

LLD: Lightweight Latency Decrease Scheme of LDPC Hard Decision Decoding for 3-D TLC NAND Flash Memory.

Debao Wei, Yongchao Wang, Hua Feng, Huqi Xiang, Liyan Qiao

IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024