Husain Parvez

Orcid: 0000-0002-6544-2454

According to our database1, Husain Parvez authored at least 21 papers between 2008 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2021
An Application Specific Reconfigurable Architecture with Reduced Area and Static Memory Cells.
J. Circuits Syst. Comput., 2021

2017
Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing.
Int. J. Reconfigurable Comput., 2017

Optimizing routing network of shared hardware design for multiple application circuits.
Proceedings of the First International Conference on Latest trends in Electrical Engineering and Computing Technologies, 2017

Logic algebra for exploiting shared SRAM-table based FPGAs for large LUT inputs.
Proceedings of the First International Conference on Latest trends in Electrical Engineering and Computing Technologies, 2017

2016
"Multi-Circuit": Automatic Generation of an Application Specific Configurable Core for Known Set of Application Circuits.
J. Circuits Syst. Comput., 2016

Exploring shared SRAM tables among NPN equivalent large LUTs in SRAM-based FPGAs.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015
An Improved Diffusion Based Placement Algorithm for Reducing Interconnect Demand in Congested Regions of FPGAs.
Int. J. Reconfigurable Comput., 2015

2014
Exploring alternate trade-offs of placement quality versus runtime in Simulated Annealing algorithm.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Design-space exploration between FPGA and ASIF.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Diffusion-Based Placement Algorithm for Reducing High Interconnect Demand in Congested Regions of FPGAs.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA.
Microelectron. J., 2013

2012
A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA.
Microprocess. Microsystems, 2012

2011
Application-Specific FPGA using heterogeneous logic blocks.
ACM Trans. Reconfigurable Technol. Syst., 2011

Exploration of Heterogeneous FPGA Architectures.
Int. J. Reconfigurable Comput., 2011

Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Application Specific FPGA Using Heterogeneous Logic Blocks.
Proceedings of the Reconfigurable Computing: Architectures, 2010

On the optimization of FPGA area depending on target applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
ASIF: Application Specific Inflexible FPGA.
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

2008
Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

A new coarse-grained FPGA architecture exploration environment.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008


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